On the Effects of Intra-gate Resistive Open Defects in Gates at Nanoscaled CMOS

Nachiket Rajderkar; Marco Ottavi; S. Pontarelli; Jie Han; F. Lombardi

doi:10.1109/DFT.2011.51

On the Effects of Intra-gate Resistive Open Defects in Gates at Nanoscaled CMOS

Nachiket Rajderkar, Marco Ottavi, S. Pontarelli, Jie Han, F. Lombardi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

1 Citation (Scopus)

Abstract

This paper presents a detailed characterization of the effects of intra-gate resistive open defects on nanoscaled CMOS gates as causing faults with timing and pattern sequence dependency. The values of the least detectable resistance are established for different feature sizes using HSPICE. It is found that as the feature size is reduced, the value of the least detectable resistance increases in the presence of a fault resulting in a delay of less than one nanosecond. The use of a low voltage testing technique is investigated for the detection of these faults. Finally, an analytical model that takes into account the gate current is proposed, this model considers the pronounced effect of the gate current at a decreasing feature size, while incurring in a small error compared with simulation results.

Original language	English
Title of host publication	IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems
DOIs	https://doi.org/10.1109/DFT.2011.51
Publication status	Published - 2011
Externally published	Yes
Event	2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011 - Marriott Pinnacle Hotel, Vancouver, Canada Duration: 3 Oct 2011 → 5 Oct 2011

Conference

Conference	2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011
Abbreviated title	DFT
Country/Territory	Canada
City	Vancouver
Period	3/10/11 → 5/10/11

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10.1109/DFT.2011.51

Cite this

@inproceedings{3cf8d640e8f84eae96c9a68626437fe1,

title = "On the Effects of Intra-gate Resistive Open Defects in Gates at Nanoscaled CMOS",

abstract = "This paper presents a detailed characterization of the effects of intra-gate resistive open defects on nanoscaled CMOS gates as causing faults with timing and pattern sequence dependency. The values of the least detectable resistance are established for different feature sizes using HSPICE. It is found that as the feature size is reduced, the value of the least detectable resistance increases in the presence of a fault resulting in a delay of less than one nanosecond. The use of a low voltage testing technique is investigated for the detection of these faults. Finally, an analytical model that takes into account the gate current is proposed, this model considers the pronounced effect of the gate current at a decreasing feature size, while incurring in a small error compared with simulation results.",

author = "Nachiket Rajderkar and Marco Ottavi and S. Pontarelli and Jie Han and F. Lombardi",

year = "2011",

doi = "10.1109/DFT.2011.51",

language = "English",

isbn = "978-1-4577-1713-0",

booktitle = "IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems",

note = "2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, DFT ; Conference date: 03-10-2011 Through 05-10-2011",

}

Rajderkar, N, Ottavi, M, Pontarelli, S, Han, J & Lombardi, F 2011, On the Effects of Intra-gate Resistive Open Defects in Gates at Nanoscaled CMOS. in IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems. 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, Vancouver, Canada, 3/10/11. https://doi.org/10.1109/DFT.2011.51

TY - GEN

T1 - On the Effects of Intra-gate Resistive Open Defects in Gates at Nanoscaled CMOS

AU - Rajderkar, Nachiket

AU - Ottavi, Marco

AU - Pontarelli, S.

AU - Han, Jie

AU - Lombardi, F.

PY - 2011

Y1 - 2011

N2 - This paper presents a detailed characterization of the effects of intra-gate resistive open defects on nanoscaled CMOS gates as causing faults with timing and pattern sequence dependency. The values of the least detectable resistance are established for different feature sizes using HSPICE. It is found that as the feature size is reduced, the value of the least detectable resistance increases in the presence of a fault resulting in a delay of less than one nanosecond. The use of a low voltage testing technique is investigated for the detection of these faults. Finally, an analytical model that takes into account the gate current is proposed, this model considers the pronounced effect of the gate current at a decreasing feature size, while incurring in a small error compared with simulation results.

AB - This paper presents a detailed characterization of the effects of intra-gate resistive open defects on nanoscaled CMOS gates as causing faults with timing and pattern sequence dependency. The values of the least detectable resistance are established for different feature sizes using HSPICE. It is found that as the feature size is reduced, the value of the least detectable resistance increases in the presence of a fault resulting in a delay of less than one nanosecond. The use of a low voltage testing technique is investigated for the detection of these faults. Finally, an analytical model that takes into account the gate current is proposed, this model considers the pronounced effect of the gate current at a decreasing feature size, while incurring in a small error compared with simulation results.

U2 - 10.1109/DFT.2011.51

DO - 10.1109/DFT.2011.51

M3 - Conference contribution

SN - 978-1-4577-1713-0

BT - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems

T2 - 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011

Y2 - 3 October 2011 through 5 October 2011

ER -

On the Effects of Intra-gate Resistive Open Defects in Gates at Nanoscaled CMOS

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