Abstract
Recently, several application areas in the test domain (e.g., burn-in and aging monitoring) started to require suitable input stimuli, able to maximize the switching activity of a certain module for a certain period of time. If the module is part of a processor, this turns into identifying a suitable sequence of instructions, able to maximize the switching activity. This paper proposes a method to attack this problem, and reports some experimental results gathered on a MIPS-like pipelined processor.
Original language | Undefined |
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Title of host publication | IEEE 21st International On-Line Testing Symposium, IOLST 2015 |
Place of Publication | USA |
Publisher | IEEE |
Pages | 34-35 |
Number of pages | 2 |
ISBN (Print) | 978-1-4673-7905-2 |
DOIs | |
Publication status | Published - Jul 2015 |
Event | 21st IEEE International On-Line Testing Symposium 2015 - Halkidiki, Greece, Halkidiki, Greece Duration: 6 Jul 2015 → 8 Jul 2015 http://tima.univ-grenoble-alpes.fr/conferences/iolts/iolts15/ |
Publication series
Name | |
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Publisher | IEEE Computer Society |
ISSN (Print) | 1942-9398 |
Conference
Conference | 21st IEEE International On-Line Testing Symposium 2015 |
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Abbreviated title | IOLTS 2015 |
Country/Territory | Greece |
City | Halkidiki |
Period | 6/07/15 → 8/07/15 |
Internet address |
Keywords
- CAES-TDT: Testable Design and Test
- EC Grant Agreement nr.: FP7/619871
- IR-101089
- METIS-318483
- EWI-27121