On the yield of compiler-based eSRAMs

X. Wang; M. Ottavi; F. Meyer; F. Lombardi

doi:10.1109/DFTVS.2004.1347820

On the yield of compiler-based eSRAMs

X. Wang, M. Ottavi, F. Meyer, F. Lombardi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

9 Citations (Scopus)

Abstract

This paper presents an extensive evaluation of the manufacturing yield of embedded SRAMs (eSRAM) which are designed using a memory compiler. The yield is evaluated by considering the different design constructs (generally referred to as kernels) that are used in defining the memory architecture through a compiler. Architectural considerations such as array size and line (word and bit) organization are analyzed. Compiler-based features of different kernels (such as required for decoding) are also treated in detail. An extensive evaluation of the provided redundancy (row, column and combined) is pursued to characterize its impact on the memory yield. Industrial data is used in the evaluation and an industrial ASIC chip (made of multiple eSRAMs) is also considered as design case.

Original language	Undefined
Title of host publication	IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Publisher	IEEE
Number of pages	9
ISBN (Print)	0-7695-2241-6
DOIs	https://doi.org/10.1109/DFTVS.2004.1347820
Publication status	Published - 8 Nov 2004
Externally published	Yes
Event	19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2004 - Cannes, France Duration: 10 Oct 2004 → 13 Oct 2004 Conference number: 19

Publication series

Name
ISSN (Print)	1550-5774

Conference

Conference	19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2004
Abbreviated title	DFT 2004
Country/Territory	France
City	Cannes
Period	10/10/04 → 13/10/04

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10.1109/DFTVS.2004.1347820

Cite this

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title = "On the yield of compiler-based eSRAMs",

abstract = "This paper presents an extensive evaluation of the manufacturing yield of embedded SRAMs (eSRAM) which are designed using a memory compiler. The yield is evaluated by considering the different design constructs (generally referred to as kernels) that are used in defining the memory architecture through a compiler. Architectural considerations such as array size and line (word and bit) organization are analyzed. Compiler-based features of different kernels (such as required for decoding) are also treated in detail. An extensive evaluation of the provided redundancy (row, column and combined) is pursued to characterize its impact on the memory yield. Industrial data is used in the evaluation and an industrial ASIC chip (made of multiple eSRAMs) is also considered as design case.",

author = "X. Wang and M. Ottavi and F. Meyer and F. Lombardi",

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doi = "10.1109/DFTVS.2004.1347820",

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AU - Wang, X.

AU - Ottavi, M.

AU - Meyer, F.

AU - Lombardi, F.

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PY - 2004/11/8

Y1 - 2004/11/8

N2 - This paper presents an extensive evaluation of the manufacturing yield of embedded SRAMs (eSRAM) which are designed using a memory compiler. The yield is evaluated by considering the different design constructs (generally referred to as kernels) that are used in defining the memory architecture through a compiler. Architectural considerations such as array size and line (word and bit) organization are analyzed. Compiler-based features of different kernels (such as required for decoding) are also treated in detail. An extensive evaluation of the provided redundancy (row, column and combined) is pursued to characterize its impact on the memory yield. Industrial data is used in the evaluation and an industrial ASIC chip (made of multiple eSRAMs) is also considered as design case.

AB - This paper presents an extensive evaluation of the manufacturing yield of embedded SRAMs (eSRAM) which are designed using a memory compiler. The yield is evaluated by considering the different design constructs (generally referred to as kernels) that are used in defining the memory architecture through a compiler. Architectural considerations such as array size and line (word and bit) organization are analyzed. Compiler-based features of different kernels (such as required for decoding) are also treated in detail. An extensive evaluation of the provided redundancy (row, column and combined) is pursued to characterize its impact on the memory yield. Industrial data is used in the evaluation and an industrial ASIC chip (made of multiple eSRAMs) is also considered as design case.

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U2 - 10.1109/DFTVS.2004.1347820

DO - 10.1109/DFTVS.2004.1347820

M3 - Conference contribution

SN - 0-7695-2241-6

BT - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

PB - IEEE

T2 - 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2004

Y2 - 10 October 2004 through 13 October 2004

ER -

On the yield of compiler-based eSRAMs

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