Optimal Positions of Twists in Global On-Chip Differential Interconnects

E. Mensink, Daniel Schinkel, Eric A.M. Klumperink, Adrianus Johannes Maria van Tuijl, Bram Nauta

    Research output: Contribution to journalArticleAcademicpeer-review

    18 Citations (Scopus)
    129 Downloads (Pure)


    Abstract—Crosstalk limits the achievable data rate of global on-chip interconnects on large CMOS ICs. This is especially the case, if low-swing signaling is used to reduce power consumption. Differential interconnects provide a solution for most crosstalk and noise sources, but not for neighbor-to-neighbor crosstalk in a data bus. This neighbor-to-neighbor crosstalk can be reduced with twists in the differential interconnect-pairs. To reduce via resistance and metal layer use, we use as few twists as possible by placing only one twist in every even interconnect-pair and only two twists in every odd interconnect-pair. Analysis shows that there are optimal positions for the twists, which depend on the termination impedances of the interconnects. Theory and measurements on a 10 mm long bus in 0.13 μm CMOS show that only one twist at 50% of the even interconnect-pairs, two twists at 30% and 70% of the odd interconnect-pairs and both a low-ohmic source and a low-ohmic load impedance are very effective in mitigating the crosstalk.
    Original languageEnglish
    Pages (from-to)438-446
    Number of pages9
    JournalIEEE transactions on very large scale integration (VLSI) systems
    Issue number4
    Publication statusPublished - 1 Apr 2007


    • IR-58143
    • EWI-9984
    • METIS-241650


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