Optimally-Placed Twists in Global On-Chip Differential Interconnects

E. Mensink; Daniel Schinkel; Eric A.M. Klumperink; Adrianus Johannes Maria van Tuijl; Bram Nauta

doi:10.1109/ESSCIR.2005.1541663

Optimally-Placed Twists in Global On-Chip Differential Interconnects

E. Mensink, Daniel Schinkel, Eric A.M. Klumperink, Adrianus Johannes Maria van Tuijl, Bram Nauta

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

4 Citations (Scopus)

156 Downloads (Pure)

Abstract

A bus-transceiver test chip in 0.13 μm CMOS achieves 3 Gb/s/ch over 10 mm long uninterrupted differential interconnect of only 0.8 μm pitch. As crosstalk would impede this high data rate, twists are used. Analysis shows that the optimal positions of the twists depend on the termination of the interconnect. Theory and measurements show that only one twist at 50% of the even interconnects, two twists at 30% and 70% of the odd interconnects and equal source and load impedances are very effective in mitigating the crosstalk.

Original language	English
Title of host publication	the European Solid-State Circuits Conference 2005 (ESSCIRC 2005)
Place of Publication	Grenoble, France
Publisher	IEEE
Pages	475-478
Number of pages	4
ISBN (Print)	0780392051
DOIs	https://doi.org/10.1109/ESSCIR.2005.1541663
Publication status	Published - Sept 2005
Event	31st European Solid-State Circuits Conference, ESSCIRC 2005 - Grenoble, France Duration: 12 Sept 2005 → 16 Sept 2005 Conference number: 31

Publication series

Name
Publisher	IEEE Press

Conference

Conference	31st European Solid-State Circuits Conference, ESSCIRC 2005
Abbreviated title	ESSCIRC
Country/Territory	France
City	Grenoble
Period	12/09/05 → 16/09/05

Keywords

IR-52599
METIS-224239
EWI-14513

Access to Document

10.1109/ESSCIR.2005.1541663

01541663Final published version, 699 KB

Cite this

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title = "Optimally-Placed Twists in Global On-Chip Differential Interconnects",

abstract = "A bus-transceiver test chip in 0.13 μm CMOS achieves 3 Gb/s/ch over 10 mm long uninterrupted differential interconnect of only 0.8 μm pitch. As crosstalk would impede this high data rate, twists are used. Analysis shows that the optimal positions of the twists depend on the termination of the interconnect. Theory and measurements show that only one twist at 50% of the even interconnects, two twists at 30% and 70% of the odd interconnects and equal source and load impedances are very effective in mitigating the crosstalk.",

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author = "E. Mensink and Daniel Schinkel and Klumperink, {Eric A.M.} and {van Tuijl}, {Adrianus Johannes Maria} and Bram Nauta",

year = "2005",

month = sep,

doi = "10.1109/ESSCIR.2005.1541663",

language = "English",

isbn = "0780392051",

publisher = "IEEE",

pages = "475--478",

booktitle = "the European Solid-State Circuits Conference 2005 (ESSCIRC 2005)",

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note = "31st European Solid-State Circuits Conference, ESSCIRC 2005, ESSCIRC ; Conference date: 12-09-2005 Through 16-09-2005",

}

Mensink, E, Schinkel, D, Klumperink, EAM, van Tuijl, AJM & Nauta, B 2005, Optimally-Placed Twists in Global On-Chip Differential Interconnects. in the European Solid-State Circuits Conference 2005 (ESSCIRC 2005). IEEE, Grenoble, France, pp. 475-478, 31st European Solid-State Circuits Conference, ESSCIRC 2005, Grenoble, France, 12/09/05. https://doi.org/10.1109/ESSCIR.2005.1541663

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T1 - Optimally-Placed Twists in Global On-Chip Differential Interconnects

AU - Mensink, E.

AU - Schinkel, Daniel

AU - Klumperink, Eric A.M.

AU - van Tuijl, Adrianus Johannes Maria

AU - Nauta, Bram

N1 - Conference code: 31

PY - 2005/9

Y1 - 2005/9

N2 - A bus-transceiver test chip in 0.13 μm CMOS achieves 3 Gb/s/ch over 10 mm long uninterrupted differential interconnect of only 0.8 μm pitch. As crosstalk would impede this high data rate, twists are used. Analysis shows that the optimal positions of the twists depend on the termination of the interconnect. Theory and measurements show that only one twist at 50% of the even interconnects, two twists at 30% and 70% of the odd interconnects and equal source and load impedances are very effective in mitigating the crosstalk.

AB - A bus-transceiver test chip in 0.13 μm CMOS achieves 3 Gb/s/ch over 10 mm long uninterrupted differential interconnect of only 0.8 μm pitch. As crosstalk would impede this high data rate, twists are used. Analysis shows that the optimal positions of the twists depend on the termination of the interconnect. Theory and measurements show that only one twist at 50% of the even interconnects, two twists at 30% and 70% of the odd interconnects and equal source and load impedances are very effective in mitigating the crosstalk.

KW - IR-52599

KW - METIS-224239

KW - EWI-14513

U2 - 10.1109/ESSCIR.2005.1541663

DO - 10.1109/ESSCIR.2005.1541663

M3 - Conference contribution

SN - 0780392051

SP - 475

EP - 478

BT - the European Solid-State Circuits Conference 2005 (ESSCIRC 2005)

PB - IEEE

CY - Grenoble, France

T2 - 31st European Solid-State Circuits Conference, ESSCIRC 2005

Y2 - 12 September 2005 through 16 September 2005

ER -

Optimally-Placed Twists in Global On-Chip Differential Interconnects

Abstract

Publication series

Conference

Keywords

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