Optimally-Placed Twists in Global On-Chip Differential Interconnects

E. Mensink, Daniel Schinkel, Eric A.M. Klumperink, Adrianus Johannes Maria van Tuijl, Bram Nauta

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    4 Citations (Scopus)
    52 Downloads (Pure)


    A bus-transceiver test chip in 0.13 μm CMOS achieves 3 Gb/s/ch over 10 mm long uninterrupted differential interconnect of only 0.8 μm pitch. As crosstalk would impede this high data rate, twists are used. Analysis shows that the optimal positions of the twists depend on the termination of the interconnect. Theory and measurements show that only one twist at 50% of the even interconnects, two twists at 30% and 70% of the odd interconnects and equal source and load impedances are very effective in mitigating the crosstalk.
    Original languageEnglish
    Title of host publicationthe European Solid-State Circuits Conference 2005 (ESSCIRC 2005)
    Place of PublicationGrenoble, France
    Number of pages4
    ISBN (Print)0780392051
    Publication statusPublished - Sep 2005
    Event31st European Solid-State Circuits Conference, ESSCIRC 2005 - Grenoble, France
    Duration: 12 Sep 200516 Sep 2005
    Conference number: 31

    Publication series

    PublisherIEEE Press


    Conference31st European Solid-State Circuits Conference, ESSCIRC 2005
    Abbreviated titleESSCIRC


    • IR-52599
    • METIS-224239
    • EWI-14513

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