Optimisation of N-channel trench MOS for power applications

R. J.E. Hueting*, G. A.M. Hurkx, E. A. Hijzen, S. W. Hodgskiss, M. Gajda

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

5 Citations (Scopus)

Abstract

The motivation of the continuous downscaling of power MOS is to attain a low on-resistance (Rds,on) for a certain breakdown voltage (BVds). Trench MOS is becoming more important for power applications below 100V. For the first time guidelines are established for obtaining an optimum trade-off between BVds and Rds,on in the voltage range up to 100V. It is shown by using simulations that for low-voltage (LV) devices <50V downscaling of the conventional device geometry is important while for high-voltage (HV) devices >50V the vertical RESURF concept in the drain is important.

Original languageEnglish
Title of host publicationESSDERC 2000 - Proceedings of the 30th European Solid-State Device Research Conference
EditorsH. Grunbacher, Gabriel M. Crean, W. A. Lane, Frank A. McCabe
PublisherIEEE Computer Society
Pages388-391
Number of pages4
ISBN (Electronic)2863322486
ISBN (Print)9782863322482
DOIs
Publication statusPublished - 1 Jan 2000
Externally publishedYes
Event30th European Solid-State Device Research Conference, ESSDERC 2000 - Cork, Ireland
Duration: 11 Sep 200013 Sep 2000
Conference number: 30

Conference

Conference30th European Solid-State Device Research Conference, ESSDERC 2000
Abbreviated titleESSDERC 2000
CountryIreland
CityCork
Period11/09/0013/09/00

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