Optimization of nitridation conditions for high quality inter-polysilicon dielectric layers

J.H. Klootwijk; H.J. Bergveld; H. van Kranenburg; P.H. Woerlee; Hans Wallinga

Optimization of nitridation conditions for high quality inter-polysilicon dielectric layers

J.H. Klootwijk
, H.J. Bergveld
, H. van Kranenburg
, P.H. Woerlee
, Hans Wallinga

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

1 Citation (Scopus)

61 Downloads (Pure)

Abstract

Nitridation of deposited high temperature oxides (HTO) was studied to form high quality inter-polysilicon dielectric layers for embedded non volatile memories. Good quality dielectric layers were obtained earlier by using an optimized deposition of polysilicon and by performing a post-dielectric anneal in a rapid thermal processor. In the present paper the quality is further improved by means of optimization of the post-dielectric anneal. The influence of temperature, time and pressure during annealing on the electrical properties is investigated. Electrical characterization by means of charge-to-breakdown (Qbd) and I-V measurements on simple capacitor structures evaluates the electrical properties of the layers. It is shown that an (optimized) rapid thermal N2O anneal leads to a very high charge to breakdown (Qbd Â¿ 25 C/cm2), low charge trapping and low leakage currents.

Original language	English
Title of host publication	ESSDERC '96: proceedings of the 26th European Solid State Device Research Conference, 1996
Place of Publication	Piscataway, NJ, USA
Publisher	IEEE
Pages	369-372
ISBN (Print)	2-86332-196-X
Publication status	Published - 9 Sept 1996
Event	26th European Solid State Device Research Conference, ESSDERC 1996 - Bologna, Italy Duration: 9 Sept 1996 → 11 Sept 1996 Conference number: 26

Publication series

Name
Publisher	IEEE

Conference

Conference	26th European Solid State Device Research Conference, ESSDERC 1996
Abbreviated title	ESSDERC
Country/Territory	Italy
City	Bologna
Period	9/09/96 → 11/09/96

Keywords

METIS-113861
IR-96429

Access to Document

05437076

http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5437076

Cite this

@inproceedings{f2144c357c814366884ceb6ff5616db9,

title = "Optimization of nitridation conditions for high quality inter-polysilicon dielectric layers",

abstract = "Nitridation of deposited high temperature oxides (HTO) was studied to form high quality inter-polysilicon dielectric layers for embedded non volatile memories. Good quality dielectric layers were obtained earlier by using an optimized deposition of polysilicon and by performing a post-dielectric anneal in a rapid thermal processor. In the present paper the quality is further improved by means of optimization of the post-dielectric anneal. The influence of temperature, time and pressure during annealing on the electrical properties is investigated. Electrical characterization by means of charge-to-breakdown (Qbd) and I-V measurements on simple capacitor structures evaluates the electrical properties of the layers. It is shown that an (optimized) rapid thermal N2O anneal leads to a very high charge to breakdown (Qbd {\^A}¿ 25 C/cm2), low charge trapping and low leakage currents.",

keywords = "METIS-113861, IR-96429",

author = "J.H. Klootwijk and H.J. Bergveld and \{van Kranenburg\}, H. and P.H. Woerlee and Hans Wallinga",

year = "1996",

month = sep,

day = "9",

language = "English",

isbn = "2-86332-196-X",

publisher = "IEEE",

pages = "369--372",

booktitle = "ESSDERC '96: proceedings of the 26th European Solid State Device Research Conference, 1996",

address = "United States",

note = "26th European Solid State Device Research Conference, ESSDERC 1996, ESSDERC ; Conference date: 09-09-1996 Through 11-09-1996",

}

Klootwijk, JH, Bergveld, HJ, van Kranenburg, H, Woerlee, PH & Wallinga, H 1996, Optimization of nitridation conditions for high quality inter-polysilicon dielectric layers. in ESSDERC '96: proceedings of the 26th European Solid State Device Research Conference, 1996. IEEE, Piscataway, NJ, USA, pp. 369-372, 26th European Solid State Device Research Conference, ESSDERC 1996, Bologna, Italy, 9/09/96. <http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5437076>

Optimization of nitridation conditions for high quality inter-polysilicon dielectric layers. / Klootwijk, J.H.; Bergveld, H.J.; van Kranenburg, H. et al.
ESSDERC '96: proceedings of the 26th European Solid State Device Research Conference, 1996. Piscataway, NJ, USA: IEEE, 1996. p. 369-372.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Optimization of nitridation conditions for high quality inter-polysilicon dielectric layers

AU - Klootwijk, J.H.

AU - Bergveld, H.J.

AU - van Kranenburg, H.

AU - Woerlee, P.H.

AU - Wallinga, Hans

N1 - Conference code: 26

PY - 1996/9/9

Y1 - 1996/9/9

N2 - Nitridation of deposited high temperature oxides (HTO) was studied to form high quality inter-polysilicon dielectric layers for embedded non volatile memories. Good quality dielectric layers were obtained earlier by using an optimized deposition of polysilicon and by performing a post-dielectric anneal in a rapid thermal processor. In the present paper the quality is further improved by means of optimization of the post-dielectric anneal. The influence of temperature, time and pressure during annealing on the electrical properties is investigated. Electrical characterization by means of charge-to-breakdown (Qbd) and I-V measurements on simple capacitor structures evaluates the electrical properties of the layers. It is shown that an (optimized) rapid thermal N2O anneal leads to a very high charge to breakdown (Qbd Â¿ 25 C/cm2), low charge trapping and low leakage currents.

AB - Nitridation of deposited high temperature oxides (HTO) was studied to form high quality inter-polysilicon dielectric layers for embedded non volatile memories. Good quality dielectric layers were obtained earlier by using an optimized deposition of polysilicon and by performing a post-dielectric anneal in a rapid thermal processor. In the present paper the quality is further improved by means of optimization of the post-dielectric anneal. The influence of temperature, time and pressure during annealing on the electrical properties is investigated. Electrical characterization by means of charge-to-breakdown (Qbd) and I-V measurements on simple capacitor structures evaluates the electrical properties of the layers. It is shown that an (optimized) rapid thermal N2O anneal leads to a very high charge to breakdown (Qbd Â¿ 25 C/cm2), low charge trapping and low leakage currents.

KW - METIS-113861

KW - IR-96429

M3 - Conference contribution

SN - 2-86332-196-X

SP - 369

EP - 372

BT - ESSDERC '96: proceedings of the 26th European Solid State Device Research Conference, 1996

PB - IEEE

CY - Piscataway, NJ, USA

T2 - 26th European Solid State Device Research Conference, ESSDERC 1996

Y2 - 9 September 1996 through 11 September 1996

ER -

Optimization of nitridation conditions for high quality inter-polysilicon dielectric layers

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