Optimized Stage Ratio of Tapered CMOS Inverters for Minimum Power and Mismatch Jitter Product

R. Dutta; T.K. Bhattacharyya; X. Gao; Eric A.M. Klumperink

doi:10.1109/VLSI.Design.2010.78

Optimized Stage Ratio of Tapered CMOS Inverters for Minimum Power and Mismatch Jitter Product

R. Dutta, T.K. Bhattacharyya, X. Gao, Eric A.M. Klumperink

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

6 Citations (Scopus)

382 Downloads (Pure)

Abstract

In this paper, an optimum stage ratio (tapering factor) for a tapered CMOS inverter chain is derived to minimize the product of power dissipation and jitter variance due to device mismatch. Analysis shows that this optimum stage ratio (2.4) is lower than that of minimum delay (3.6) and minimum power-delay (6.35) product. This analysis is verified by simulation results using standard 180 nm as well as 90 nm CMOS technology. Knowledge of the optimum stage ratio helps to design low power low mismatch jitter buffers for multi phase clock generation circuits that can drive large load capacitances.

Original language	English
Title of host publication	23th International Conference on VLSI Design, VLSID 2010
Place of Publication	Piscataway
Publisher	IEEE
Pages	152-157
Number of pages	6
ISBN (Print)	978-1-4244-5541-6
DOIs	https://doi.org/10.1109/VLSI.Design.2010.78
Publication status	Published - 6 Jan 2010
Event	23th International Conference on VLSI Design, VLSID 2010 - Bangalore, India Duration: 3 Jan 2010 → 7 Jan 2010 Conference number: 23

Conference

Conference	23th International Conference on VLSI Design, VLSID 2010
Abbreviated title	VLSID
Country/Territory	India
City	Bangalore
Period	3/01/10 → 7/01/10

Keywords

METIS-275611
CMOS inverter
IR-75789
multiphase clock
EWI-18150
stage ratio
mismatch jitter
Tapering factor
figure of meri
Low power

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title = "Optimized Stage Ratio of Tapered CMOS Inverters for Minimum Power and Mismatch Jitter Product",

abstract = "In this paper, an optimum stage ratio (tapering factor) for a tapered CMOS inverter chain is derived to minimize the product of power dissipation and jitter variance due to device mismatch. Analysis shows that this optimum stage ratio (2.4) is lower than that of minimum delay (3.6) and minimum power-delay (6.35) product. This analysis is verified by simulation results using standard 180 nm as well as 90 nm CMOS technology. Knowledge of the optimum stage ratio helps to design low power low mismatch jitter buffers for multi phase clock generation circuits that can drive large load capacitances.",

keywords = "METIS-275611, CMOS inverter, IR-75789, multiphase clock, EWI-18150, stage ratio, mismatch jitter, Tapering factor, figure of meri, Low power",

author = "R. Dutta and T.K. Bhattacharyya and X. Gao and Klumperink, {Eric A.M.}",

year = "2010",

month = jan,

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doi = "10.1109/VLSI.Design.2010.78",

language = "English",

isbn = "978-1-4244-5541-6",

pages = "152--157",

booktitle = "23th International Conference on VLSI Design, VLSID 2010",

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note = "23th International Conference on VLSI Design, VLSID 2010, VLSID ; Conference date: 03-01-2010 Through 07-01-2010",

}

Dutta, R, Bhattacharyya, TK, Gao, X & Klumperink, EAM 2010, Optimized Stage Ratio of Tapered CMOS Inverters for Minimum Power and Mismatch Jitter Product. in 23th International Conference on VLSI Design, VLSID 2010. IEEE, Piscataway, pp. 152-157, 23th International Conference on VLSI Design, VLSID 2010, Bangalore, India, 3/01/10. https://doi.org/10.1109/VLSI.Design.2010.78

TY - GEN

T1 - Optimized Stage Ratio of Tapered CMOS Inverters for Minimum Power and Mismatch Jitter Product

AU - Dutta, R.

AU - Bhattacharyya, T.K.

AU - Gao, X.

AU - Klumperink, Eric A.M.

N1 - Conference code: 23

PY - 2010/1/6

Y1 - 2010/1/6

N2 - In this paper, an optimum stage ratio (tapering factor) for a tapered CMOS inverter chain is derived to minimize the product of power dissipation and jitter variance due to device mismatch. Analysis shows that this optimum stage ratio (2.4) is lower than that of minimum delay (3.6) and minimum power-delay (6.35) product. This analysis is verified by simulation results using standard 180 nm as well as 90 nm CMOS technology. Knowledge of the optimum stage ratio helps to design low power low mismatch jitter buffers for multi phase clock generation circuits that can drive large load capacitances.

AB - In this paper, an optimum stage ratio (tapering factor) for a tapered CMOS inverter chain is derived to minimize the product of power dissipation and jitter variance due to device mismatch. Analysis shows that this optimum stage ratio (2.4) is lower than that of minimum delay (3.6) and minimum power-delay (6.35) product. This analysis is verified by simulation results using standard 180 nm as well as 90 nm CMOS technology. Knowledge of the optimum stage ratio helps to design low power low mismatch jitter buffers for multi phase clock generation circuits that can drive large load capacitances.

KW - METIS-275611

KW - CMOS inverter

KW - IR-75789

KW - multiphase clock

KW - EWI-18150

KW - stage ratio

KW - mismatch jitter

KW - Tapering factor

KW - figure of meri

KW - Low power

U2 - 10.1109/VLSI.Design.2010.78

DO - 10.1109/VLSI.Design.2010.78

M3 - Conference contribution

SN - 978-1-4244-5541-6

SP - 152

EP - 157

BT - 23th International Conference on VLSI Design, VLSID 2010

PB - IEEE

CY - Piscataway

T2 - 23th International Conference on VLSI Design, VLSID 2010

Y2 - 3 January 2010 through 7 January 2010

ER -

Optimized Stage Ratio of Tapered CMOS Inverters for Minimum Power and Mismatch Jitter Product

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Conference

Keywords

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