Optimizing scrubbing by netlist analysis for FPGA configuration bit classification and floorplanning

Bernhard Schmidt, Daniel Ziener*, Jürgen Teich, Christian Zöllner

*Corresponding author for this work

    Research output: Contribution to journalArticleAcademicpeer-review

    1 Citation (Scopus)
    2 Downloads (Pure)

    Abstract

    Existing scrubbing techniques for SEU mitigation on FPGAs do not guarantee an error-free operation after SEU recovering if the affected configuration bits do belong to feedback loops of the implemented circuits. In this paper, we a) provide a netlist-based circuit analysis technique to distinguish so-called critical configuration bits from essential bits in order to identify configuration bits which will need also state-restoring actions after a recovered SEU and which not. Furthermore, b) an alternative classification approach using fault injection is developed in order to compare both classification techniques. Moreover, c) we will propose a floorplanning approach for reducing the effective number of scrubbed frames and d), experimental results will give evidence that our optimization methodology not only allows to detect errors earlier but also to minimize the Mean-Time-To-Repair (MTTR) of a circuit considerably. In particular, we show that by using our approach, the MTTR for datapath-intensive circuits can be reduced by up to 48.5% in comparison to standard approaches.

    Original languageEnglish
    Pages (from-to)98-108
    Number of pages11
    JournalIntegration, the VLSI Journal
    Volume59
    DOIs
    Publication statusPublished - 1 Sep 2017

    Keywords

    • Configuration bit partitioning
    • Fault injection
    • Floorplanning
    • FPGA scrubbing
    • Single Event Upsets

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