Abstract
This paper presents an analysis of outphasing class-E Power Amplifiers (OEPAs), using load-pull analyses of single class-E PAs. This analysis is subsequently used to rotate and shift power contours and rotate the efficiency contours to improve the efficiency of OEPAs at deep power back-off, to improve the Output Power Dynamic Range (OPDR) and to reduce switch voltage stress. To validate the theory a 65nm CMOS prototype, using a pcb transmission-line based power combiner was implemented. The OEPA provides +20.1dBm output power from VDD=1.25V at 1.8GHz with more than 65% Drain Efficiency (DE) and 60% Power Added Efficiency (PAE). The presented technique enables more than 49dB OPDR and 37% DE and 22%PAE at 12dB back-off with reduced switch voltage stress.
Original language | English |
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Pages (from-to) | 1374-1386 |
Number of pages | 13 |
Journal | IEEE journal of solid-state circuits |
Volume | 53 |
Issue number | 5 |
Early online date | 23 Jan 0002 |
DOIs | |
Publication status | Published - 1 May 2018 |