TY - GEN
T1 - Overview of the 4S project
AU - Smit, Gerardus Johannes Maria
AU - Schuler, Eberhard
AU - Becker, Jürgen
AU - Quevremont, Jérôme
AU - Brugger, Werner
N1 - Imported from CHAMELEON.xml
PY - 2005/11
Y1 - 2005/11
N2 - In this paper an overview of the EU-FP6 "Smart Chips for Smart Surroundings" (4S) project is given. The overall mission of the 4S project is to define and develop efficient (ultra low-power), flexible, reconfigurable core building blocks, including the supporting tools, for future ambient systems. Dynamic reconfiguration offers the flexibility and adaptability needed for future ambient devices, it provides the efficiency needed for these systems, it enables systems that can adapt to rapidly changing environmental conditions, it enables communication over heterogeneous wireless networks, and it
reduces risks: reconfigurable systems can adapt to standards that may vary from place to place or standards that have changed during and after product development.
AB - In this paper an overview of the EU-FP6 "Smart Chips for Smart Surroundings" (4S) project is given. The overall mission of the 4S project is to define and develop efficient (ultra low-power), flexible, reconfigurable core building blocks, including the supporting tools, for future ambient systems. Dynamic reconfiguration offers the flexibility and adaptability needed for future ambient devices, it provides the efficiency needed for these systems, it enables systems that can adapt to rapidly changing environmental conditions, it enables communication over heterogeneous wireless networks, and it
reduces risks: reconfigurable systems can adapt to standards that may vary from place to place or standards that have changed during and after product development.
KW - EC Grant Agreement nr.: FP6/001908
KW - EWI-1469
KW - CAES-EEA: Efficient Embedded Architectures
KW - METIS-229228
KW - IR-54762
U2 - 10.1109/ISSOC.2005.1595647
DO - 10.1109/ISSOC.2005.1595647
M3 - Conference contribution
SN - 0-7803-9294-9
SP - 70
EP - 73
BT - Proceedings of the International Symposium on System-on-Chip (SoC 2005)
PB - IEEE
CY - Piscataway, NJ, USA
T2 - International Symposium on System-on-Chip, SoC 2005
Y2 - 14 November 2005 through 17 November 2005
ER -