This paper presents an overview of a tool chain to support a transformational design methodology. The tool can be used to compile code written in a high level source language, like C, to a coarse grain reconfigurable architecture. The source code is first translated into a Control Data Flow Graph (CDFG). A Control Dataflow Graph contains not only the dataflow operations (e.g. arithmetic or logical operations on data) but also control flow operations (e.g. operators for loop and if then else constructs). The CDFG is minimized using a set of behavior preserving transformations such as dependency analysis, common sub-expression elimination, etc. After applying graph clustering, scheduling and allocation transformations on this minimized graph, it can be mapped onto the target architecture.
|Title of host publication||ERSA'04|
|Subtitle of host publication||proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms|
|Place of Publication||Arthens, GA|
|Number of pages||7|
|Publication status||Published - Jun 2004|
|Event||2004 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA '04 - Las Vegas, United States|
Duration: 21 Jun 2004 → 24 Jun 2004
|Conference||2004 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA '04|
|Period||21/06/04 → 24/06/04|
- CAES-EEA: Efficient Embedded Architectures
Smit, G. J. M., Rosien, M. A. J., Guo, Y., & Heysters, P. M. (2004). Overview of the tool-flow for the Montium Processing Tile. In ERSA'04: proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (pp. 45-51). Arthens, GA: CSREA Press.