Overview of the tool-flow for the Montium Processing Tile

Gerardus Johannes Maria Smit, M.A.J. Rosien, Y. Guo, P.M. Heysters

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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    Abstract

    This paper presents an overview of a tool chain to support a transformational design methodology. The tool can be used to compile code written in a high level source language, like C, to a coarse grain reconfigurable architecture. The source code is first translated into a Control Data Flow Graph (CDFG). A Control Dataflow Graph contains not only the dataflow operations (e.g. arithmetic or logical operations on data) but also control flow operations (e.g. operators for loop and if then else constructs). The CDFG is minimized using a set of behavior preserving transformations such as dependency analysis, common sub-expression elimination, etc. After applying graph clustering, scheduling and allocation transformations on this minimized graph, it can be mapped onto the target architecture.
    Original languageEnglish
    Title of host publicationERSA'04
    Subtitle of host publicationproceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms
    Place of Publication Arthens, GA
    PublisherCSREA Press
    Pages45-51
    Number of pages7
    ISBN (Print)1-932415-42-4
    Publication statusPublished - Jun 2004
    Event2004 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA '04 - Las Vegas, United States
    Duration: 21 Jun 200424 Jun 2004

    Conference

    Conference2004 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA '04
    Abbreviated titleERSA
    CountryUnited States
    CityLas Vegas
    Period21/06/0424/06/04

    Fingerprint

    Tile
    Data flow graphs
    Processing
    Reconfigurable architectures
    Flow control
    Scheduling

    Keywords

    • CAES-EEA: Efficient Embedded Architectures
    • METIS-221626
    • EWI-1501
    • IR-49365

    Cite this

    Smit, G. J. M., Rosien, M. A. J., Guo, Y., & Heysters, P. M. (2004). Overview of the tool-flow for the Montium Processing Tile. In ERSA'04: proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (pp. 45-51). Arthens, GA: CSREA Press.
    Smit, Gerardus Johannes Maria ; Rosien, M.A.J. ; Guo, Y. ; Heysters, P.M. / Overview of the tool-flow for the Montium Processing Tile. ERSA'04: proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms. Arthens, GA : CSREA Press, 2004. pp. 45-51
    @inproceedings{8c316f6edbf64be892fc735419b32b37,
    title = "Overview of the tool-flow for the Montium Processing Tile",
    abstract = "This paper presents an overview of a tool chain to support a transformational design methodology. The tool can be used to compile code written in a high level source language, like C, to a coarse grain reconfigurable architecture. The source code is first translated into a Control Data Flow Graph (CDFG). A Control Dataflow Graph contains not only the dataflow operations (e.g. arithmetic or logical operations on data) but also control flow operations (e.g. operators for loop and if then else constructs). The CDFG is minimized using a set of behavior preserving transformations such as dependency analysis, common sub-expression elimination, etc. After applying graph clustering, scheduling and allocation transformations on this minimized graph, it can be mapped onto the target architecture.",
    keywords = "CAES-EEA: Efficient Embedded Architectures, METIS-221626, EWI-1501, IR-49365",
    author = "Smit, {Gerardus Johannes Maria} and M.A.J. Rosien and Y. Guo and P.M. Heysters",
    note = "Imported from CHAMELEON.xml",
    year = "2004",
    month = "6",
    language = "English",
    isbn = "1-932415-42-4",
    pages = "45--51",
    booktitle = "ERSA'04",
    publisher = "CSREA Press",

    }

    Smit, GJM, Rosien, MAJ, Guo, Y & Heysters, PM 2004, Overview of the tool-flow for the Montium Processing Tile. in ERSA'04: proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms. CSREA Press, Arthens, GA, pp. 45-51, 2004 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA '04, Las Vegas, United States, 21/06/04.

    Overview of the tool-flow for the Montium Processing Tile. / Smit, Gerardus Johannes Maria; Rosien, M.A.J.; Guo, Y.; Heysters, P.M.

    ERSA'04: proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms. Arthens, GA : CSREA Press, 2004. p. 45-51.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    TY - GEN

    T1 - Overview of the tool-flow for the Montium Processing Tile

    AU - Smit, Gerardus Johannes Maria

    AU - Rosien, M.A.J.

    AU - Guo, Y.

    AU - Heysters, P.M.

    N1 - Imported from CHAMELEON.xml

    PY - 2004/6

    Y1 - 2004/6

    N2 - This paper presents an overview of a tool chain to support a transformational design methodology. The tool can be used to compile code written in a high level source language, like C, to a coarse grain reconfigurable architecture. The source code is first translated into a Control Data Flow Graph (CDFG). A Control Dataflow Graph contains not only the dataflow operations (e.g. arithmetic or logical operations on data) but also control flow operations (e.g. operators for loop and if then else constructs). The CDFG is minimized using a set of behavior preserving transformations such as dependency analysis, common sub-expression elimination, etc. After applying graph clustering, scheduling and allocation transformations on this minimized graph, it can be mapped onto the target architecture.

    AB - This paper presents an overview of a tool chain to support a transformational design methodology. The tool can be used to compile code written in a high level source language, like C, to a coarse grain reconfigurable architecture. The source code is first translated into a Control Data Flow Graph (CDFG). A Control Dataflow Graph contains not only the dataflow operations (e.g. arithmetic or logical operations on data) but also control flow operations (e.g. operators for loop and if then else constructs). The CDFG is minimized using a set of behavior preserving transformations such as dependency analysis, common sub-expression elimination, etc. After applying graph clustering, scheduling and allocation transformations on this minimized graph, it can be mapped onto the target architecture.

    KW - CAES-EEA: Efficient Embedded Architectures

    KW - METIS-221626

    KW - EWI-1501

    KW - IR-49365

    M3 - Conference contribution

    SN - 1-932415-42-4

    SP - 45

    EP - 51

    BT - ERSA'04

    PB - CSREA Press

    CY - Arthens, GA

    ER -

    Smit GJM, Rosien MAJ, Guo Y, Heysters PM. Overview of the tool-flow for the Montium Processing Tile. In ERSA'04: proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms. Arthens, GA: CSREA Press. 2004. p. 45-51