Parallel graph reduction for divide-and-conquer applications -- Part II: program performance

Pieter H. Hartel, Willem G. Vree

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    Abstract

    An extensible machine architecture is devised to efficiently support a parallel reduction model of computation. The organisation of the machine is designed to match the behaviour of the application programs. A pilot implementation of the architecture is used to obtain an execution profile of the various applications. These profiles are used with a performance model to calculate optimal schedules of the applications. The resulting speedup figures give an upper bound for the performance gain that may be attained on a full implementation of the architecture. The most important result is that each application allows for a processor utilisation of over 50% to be attained on our parallel architecture.
    Original languageUndefined
    Place of PublicationAmsterdam, the Netherlands
    PublisherUniversity of Amsterdam
    Number of pages27
    Publication statusPublished - Dec 1988

    Publication series

    NamePRM project internal report
    PublisherUniversity of Amsterdam
    No.D-20

    Keywords

    • IR-68208
    • EWI-16202

    Cite this

    Hartel, P. H., & Vree, W. G. (1988). Parallel graph reduction for divide-and-conquer applications -- Part II: program performance. (PRM project internal report; No. D-20). Amsterdam, the Netherlands: University of Amsterdam.