Phase-locked loop including sampling phase detector and charge pump with pulse width control

X. Gao; Eric A.M. Klumperink; Bram Nauta; Mounhir Bohsali; Ali Kiaei; Gerard Socci; Ali Djabbari

Phase-locked loop including sampling phase detector and charge pump with pulse width control

X. Gao (Inventor), Eric A.M. Klumperink (Inventor), Bram Nauta (Inventor), Mounhir Bohsali (Inventor), Ali Kiaei (Inventor), Gerard Socci (Inventor), Ali Djabbari (Inventor)

Research output: Patent

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Abstract

Phase-locked loop (PLL) circuitry in which a sampling phase detector samples the output signal in accordance with the reference signal and a frequency detector detects the output signal frequency in accordance with the reference signal.

Original language	Undefined
Patent number	US7737743B1
Priority date	15/06/10
Publication status	Published - 15 Jun 2010

Keywords

METIS-277812
IR-75786
EWI-19429

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http://v3.espacenet.com/publicationDetails/biblio?CC=US&NR=7737743B1&KC=B1&FT=D&date=20100615&DB=EPODOC&locale=en_EP

1 Patent

Phase-locked loop including sampling phase detector and charge pump with pulse width control
Gao, X. (Inventor), Klumperink, E. A. M. (Inventor), Nauta, B. (Inventor), Bohsali, M. (Inventor), Kiaei, A. (Inventor), Socci, G. (Inventor) & Djabbari, A. (Inventor), 7 Mar 2008, (Submitted) Patent No. US20080044522, Priority date 15 Jun 2010
Research output: Patent

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Cite this

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title = "Phase-locked loop including sampling phase detector and charge pump with pulse width control",

abstract = "Phase-locked loop (PLL) circuitry in which a sampling phase detector samples the output signal in accordance with the reference signal and a frequency detector detects the output signal frequency in accordance with the reference signal.",

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author = "X. Gao and Klumperink, {Eric A.M.} and Bram Nauta and Mounhir Bohsali and Ali Kiaei and Gerard Socci and Ali Djabbari",

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T1 - Phase-locked loop including sampling phase detector and charge pump with pulse width control

AU - Gao, X.

AU - Klumperink, Eric A.M.

AU - Nauta, Bram

AU - Bohsali, Mounhir

AU - Kiaei, Ali

AU - Socci, Gerard

AU - Djabbari, Ali

PY - 2010/6/15

Y1 - 2010/6/15

N2 - Phase-locked loop (PLL) circuitry in which a sampling phase detector samples the output signal in accordance with the reference signal and a frequency detector detects the output signal frequency in accordance with the reference signal.

AB - Phase-locked loop (PLL) circuitry in which a sampling phase detector samples the output signal in accordance with the reference signal and a frequency detector detects the output signal frequency in accordance with the reference signal.

KW - METIS-277812

KW - IR-75786

KW - EWI-19429

M3 - Patent

M1 - US7737743B1

ER -