Abstract
Phase-locked loop (PLL) circuitry in which a sampling phase detector samples the output signal in accordance with the reference signal and a frequency detector detects the output signal frequency in accordance with the reference signal.
Original language | Undefined |
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Patent number | US7737743B1 |
Priority date | 15/06/10 |
Publication status | Published - 15 Jun 2010 |
Keywords
- METIS-277812
- IR-75786
- EWI-19429