Phase-locked loop including sampling phase detector and charge pump with pulse width control

X. Gao; Eric A.M. Klumperink; Bram Nauta; M. Bohsali; A. Kiaei; G. Socci; A. Djabbari

Phase-locked loop including sampling phase detector and charge pump with pulse width control

X. Gao (Inventor), Eric A.M. Klumperink (Inventor), Bram Nauta (Inventor), M. Bohsali (Inventor), A. Kiaei (Inventor), G. Socci (Inventor), A. Djabbari (Inventor)

Research output: Patent

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Abstract

Phase-locked loop (PLL) circuitry in which a sampling phase detector samples the output signal in accordance with the reference signal and a frequency detector detects the output signal frequency in accordance with the reference signal.

Original language	Undefined
Patent number	US20080044522
Priority date	15/06/10
Publication status	Submitted - 7 Mar 2008

Keywords

METIS-270685
EWI-15038

Access to Document

US7737743B1
open

http://v3.espacenet.com/publicationDetails/biblio?DB=EPODOC&adjacent=true&locale=en_EP&FT=D&date=20100615&CC=US&NR=7737743B1&KC=B1

Cite this

Gao, X., Klumperink, E. A. M., Nauta, B., Bohsali, M., Kiaei, A., Socci, G., & Djabbari, A. (2008). Phase-locked loop including sampling phase detector and charge pump with pulse width control. Manuscript submitted for publication. (Patent No. US20080044522). http://v3.espacenet.com/publicationDetails/biblio?DB=EPODOC&adjacent=true&locale=en_EP&FT=D&date=20100615&CC=US&NR=7737743B1&KC=B1

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abstract = "Phase-locked loop (PLL) circuitry in which a sampling phase detector samples the output signal in accordance with the reference signal and a frequency detector detects the output signal frequency in accordance with the reference signal.",

keywords = "METIS-270685, EWI-15038",

author = "X. Gao and Klumperink, {Eric A.M.} and Bram Nauta and M. Bohsali and A. Kiaei and G. Socci and A. Djabbari",

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T1 - Phase-locked loop including sampling phase detector and charge pump with pulse width control

AU - Gao, X.

AU - Klumperink, Eric A.M.

AU - Nauta, Bram

AU - Bohsali, M.

AU - Kiaei, A.

AU - Socci, G.

AU - Djabbari, A.

PY - 2008/3/7

Y1 - 2008/3/7

N2 - Phase-locked loop (PLL) circuitry in which a sampling phase detector samples the output signal in accordance with the reference signal and a frequency detector detects the output signal frequency in accordance with the reference signal.

AB - Phase-locked loop (PLL) circuitry in which a sampling phase detector samples the output signal in accordance with the reference signal and a frequency detector detects the output signal frequency in accordance with the reference signal.

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KW - EWI-15038

M3 - Patent

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