Phase-locked loop including sampling phase detector and charge pump with pulse width control

Xiang Gao; Eric A.M. Klumperink; Bram Nauta; Mounhir Bohsali; Ali Kiaei; Gerard Socci; Ali Djabbari

Phase-locked loop including sampling phase detector and charge pump with pulse width control

Xiang Gao (Inventor)
, Eric A.M. Klumperink (Inventor)
, Bram Nauta (Inventor)
, Mounhir Bohsali (Inventor)
, Ali Kiaei (Inventor)
, Gerard Socci (Inventor)
, Ali Djabbari (Inventor)

Research output: Patent

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Abstract

Phase-locked loop (PLL) circuitry in which a sampling phase detector samples the output signal in accordance with the reference signal and a frequency detector detects the output signal frequency in accordance with the reference signal.

Original language	English
Patent number	US7737743B1
Priority date	15/06/10
Filing date	7/03/08
Publication status	Published - 15 Jun 2010

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US7737743B1Final published version, 506 KB

https://patents.google.com/patent/US7737743B1/en

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Phase-locked loop including sampling phase detector and charge pump with pulse width control
Gao, X. (Inventor), Klumperink, E. A. M. (Inventor), Nauta, B. (Inventor), Bohsali, M. (Inventor), Kiaei, A. (Inventor), Socci, G. (Inventor) & Djabbari, A. (Inventor), 15 Jun 2010, Patent No. US7737743B1, 7 Mar 2008, Priority date 15 Jun 2010
Research output: Patent

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title = "Phase-locked loop including sampling phase detector and charge pump with pulse width control",

abstract = "Phase-locked loop (PLL) circuitry in which a sampling phase detector samples the output signal in accordance with the reference signal and a frequency detector detects the output signal frequency in accordance with the reference signal.",

author = "Xiang Gao and Klumperink, \{Eric A.M.\} and Bram Nauta and Mounhir Bohsali and Ali Kiaei and Gerard Socci and Ali Djabbari",

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T1 - Phase-locked loop including sampling phase detector and charge pump with pulse width control

AU - Gao, Xiang

AU - Klumperink, Eric A.M.

AU - Nauta, Bram

AU - Bohsali, Mounhir

AU - Kiaei, Ali

AU - Socci, Gerard

AU - Djabbari, Ali

PY - 2010/6/15

Y1 - 2010/6/15

N2 - Phase-locked loop (PLL) circuitry in which a sampling phase detector samples the output signal in accordance with the reference signal and a frequency detector detects the output signal frequency in accordance with the reference signal.

AB - Phase-locked loop (PLL) circuitry in which a sampling phase detector samples the output signal in accordance with the reference signal and a frequency detector detects the output signal frequency in accordance with the reference signal.

M3 - Patent

M1 - US7737743B1

Y2 - 2008/03/07

ER -

Phase-locked loop including sampling phase detector and charge pump with pulse width control

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Research output

Phase-locked loop including sampling phase detector and charge pump with pulse width control

Cite this