Phase-Locked-Loop With Reduced Clock Jitter

Bram Nauta (Inventor), R.C.H. van de Beek (Inventor), Cicero S. Vaucher (Inventor)

    Research output: Patent

    12 Downloads (Pure)

    Abstract

    The present invention relates to a phase-locked-loop (PLL) circuit and a method for controlling such a PLL circuit, wherein the frequency of an input reference signal and the frequency of a feedback signal derived from an output oscillation signal are divided by a predetermined rate to thereby reduce the frequency at a phase detection means (1) of the PLL circuit. The dividing step is inhibited in response to a detection of a phase-locked-state of the PLL circuit. Thus, after phase-lock has been achieved, extra reference dividers (6) added to decrease the comparison frequency are removed from the loop to thereby enable increase in the loop bandwidths and decrease in the dividing ratio within the loop.
    Original languageUndefined
    Patent numberEP1474872
    Publication statusPublished - 23 Nov 2005

    Keywords

    • IR-75675
    • EWI-19349

    Cite this

    Nauta, B., van de Beek, R. C. H., & Vaucher, C. S. (2005). Phase-Locked-Loop With Reduced Clock Jitter. (Patent No. EP1474872).
    Nauta, Bram (Inventor) ; van de Beek, R.C.H. (Inventor) ; Vaucher, Cicero S. (Inventor). / Phase-Locked-Loop With Reduced Clock Jitter. Patent No.: EP1474872.
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    title = "Phase-Locked-Loop With Reduced Clock Jitter",
    abstract = "The present invention relates to a phase-locked-loop (PLL) circuit and a method for controlling such a PLL circuit, wherein the frequency of an input reference signal and the frequency of a feedback signal derived from an output oscillation signal are divided by a predetermined rate to thereby reduce the frequency at a phase detection means (1) of the PLL circuit. The dividing step is inhibited in response to a detection of a phase-locked-state of the PLL circuit. Thus, after phase-lock has been achieved, extra reference dividers (6) added to decrease the comparison frequency are removed from the loop to thereby enable increase in the loop bandwidths and decrease in the dividing ratio within the loop.",
    keywords = "IR-75675, EWI-19349",
    author = "Bram Nauta and {van de Beek}, R.C.H. and Vaucher, {Cicero S.}",
    year = "2005",
    month = "11",
    day = "23",
    language = "Undefined",
    type = "Patent",
    note = "EP1474872",

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    Nauta, B, van de Beek, RCH & Vaucher, CS 2005, Phase-Locked-Loop With Reduced Clock Jitter, Patent No. EP1474872.

    Phase-Locked-Loop With Reduced Clock Jitter. / Nauta, Bram (Inventor); van de Beek, R.C.H. (Inventor); Vaucher, Cicero S. (Inventor).

    Patent No.: EP1474872.

    Research output: Patent

    TY - PAT

    T1 - Phase-Locked-Loop With Reduced Clock Jitter

    AU - Nauta, Bram

    AU - van de Beek, R.C.H.

    AU - Vaucher, Cicero S.

    PY - 2005/11/23

    Y1 - 2005/11/23

    N2 - The present invention relates to a phase-locked-loop (PLL) circuit and a method for controlling such a PLL circuit, wherein the frequency of an input reference signal and the frequency of a feedback signal derived from an output oscillation signal are divided by a predetermined rate to thereby reduce the frequency at a phase detection means (1) of the PLL circuit. The dividing step is inhibited in response to a detection of a phase-locked-state of the PLL circuit. Thus, after phase-lock has been achieved, extra reference dividers (6) added to decrease the comparison frequency are removed from the loop to thereby enable increase in the loop bandwidths and decrease in the dividing ratio within the loop.

    AB - The present invention relates to a phase-locked-loop (PLL) circuit and a method for controlling such a PLL circuit, wherein the frequency of an input reference signal and the frequency of a feedback signal derived from an output oscillation signal are divided by a predetermined rate to thereby reduce the frequency at a phase detection means (1) of the PLL circuit. The dividing step is inhibited in response to a detection of a phase-locked-state of the PLL circuit. Thus, after phase-lock has been achieved, extra reference dividers (6) added to decrease the comparison frequency are removed from the loop to thereby enable increase in the loop bandwidths and decrease in the dividing ratio within the loop.

    KW - IR-75675

    KW - EWI-19349

    M3 - Patent

    M1 - EP1474872

    ER -

    Nauta B, van de Beek RCH, Vaucher CS, inventors. Phase-Locked-Loop With Reduced Clock Jitter. EP1474872. 2005 Nov 23.