Physics-based stability analysis of MOS transistors

A. Ferrara, P.G. Steeneken, B.K. Boksteen, A. Heringa, A.J. Scholten, Jurriaan Schmitz, Raymond Josephus Engelbart Hueting

    Research output: Contribution to journalArticleAcademicpeer-review

    Abstract

    In this work, a physics-based model is derived based on a linearization procedure for investigating the electrical, thermal and electro-thermal instability of power metal–oxide–semiconductor (MOS) transistors. The proposed model can be easily interfaced with a circuit or device simulator to perform a failure analysis, making it particularly useful for power transistors. Furthermore, it allows mapping the failure points on a three-dimensional (3D) space defined by the gate-width normalized drain current, drain voltage and junction temperature. This leads to the definition of the Safe Operating Volume (SOV), a powerful frame work for making failure predictions and determining the main root of instability (electrical, thermal or electro-thermal) in different bias and operating conditions. A comparison between the modeled and the measured SOV of silicon-on-insulator (SOI) LDMOS transistors is reported to support the validity of the proposed stability analysis.
    Original languageEnglish
    Pages (from-to)28-34
    Number of pages7
    JournalSolid-state electronics
    Volume113
    DOIs
    Publication statusPublished - 10 Jun 2015

    Keywords

    • Power MOSFETSilicon-on-insulator (SOI)Safe Operating Area (SOA)Safe Operating Volume (SOV)Stability factorFailure function
    • EWI-26279

    Fingerprint

    Dive into the research topics of 'Physics-based stability analysis of MOS transistors'. Together they form a unique fingerprint.

    Cite this