Abstract
| Original language | Undefined |
|---|---|
| Title of host publication | Proceedings of the 27th IEEE International Parallel and Distributed Processing Symposium (IPDPS 2013) - 20th Reconfigurable Architectures Workshop (RAW 2013) |
| Place of Publication | USA |
| Publisher | IEEE Computer Society |
| Pages | 212-221 |
| Number of pages | 10 |
| ISBN (Print) | 978-0-7695-4979-8 |
| DOIs | |
| Publication status | Published - 21 May 2013 |
| Event | 20th Reconfigurable Architectures Workshop, RAW 2013 - Boston, United States Duration: 20 May 2013 → 24 May 2013 Conference number: 20 http://www.ece.lsu.edu/vaidy/raw13/ |
Publication series
| Name | |
|---|---|
| Publisher | IEEE Computer Society |
Workshop
| Workshop | 20th Reconfigurable Architectures Workshop, RAW 2013 |
|---|---|
| Abbreviated title | RAW |
| Country | United States |
| City | Boston |
| Period | 20/05/13 → 24/05/13 |
| Internet address |
Keywords
- EWI-23363
- IR-86199
- METIS-297648
- CAES-EEA: Efficient Embedded Architectures
Cite this
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Portable memory consistency for software managed distributed memory in many-core SoC. / Rutgers, J.H.; Bekooij, Marco Jan Gerrit; Smit, Gerardus Johannes Maria.
Proceedings of the 27th IEEE International Parallel and Distributed Processing Symposium (IPDPS 2013) - 20th Reconfigurable Architectures Workshop (RAW 2013). USA : IEEE Computer Society, 2013. p. 212-221.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
TY - GEN
T1 - Portable memory consistency for software managed distributed memory in many-core SoC
AU - Rutgers, J.H.
AU - Bekooij, Marco Jan Gerrit
AU - Smit, Gerardus Johannes Maria
N1 - 10.1109/IPDPSW.2013.14
PY - 2013/5/21
Y1 - 2013/5/21
N2 - Porting software to different platforms can require modifications of the application. One of the issues is that the targeted hardware supports another memory consistency model. As a consequence, the completion order of reads and writes in a multi-threaded application can change, which may result in improper synchronization. For example, a processor with out-of-order execution could break synchronization if proper fence instructions are missing. Such a bug can cause sporadic errors, which are hard to debug. This paper presents an approach that makes applications independent of the memory model of the hardware, hence they can be compiled to hardware with any memory architecture. The key is having a memory model that only guarantees the most fundamental orderings of reads and writes, and annotations to specify additional ordering constraints. As a result, tooling can transparently and properly implement fences, cache flushes, etc. when appropriate, without losing flexibility of the hardware design. In a case study, several SPLASH-2 applications are run on a 32-core software cache coherent MicroBlaze system in FPGA. Moreover, this approach also allows mapping to scratch-pad memories and a distributed shared memory architecture.
AB - Porting software to different platforms can require modifications of the application. One of the issues is that the targeted hardware supports another memory consistency model. As a consequence, the completion order of reads and writes in a multi-threaded application can change, which may result in improper synchronization. For example, a processor with out-of-order execution could break synchronization if proper fence instructions are missing. Such a bug can cause sporadic errors, which are hard to debug. This paper presents an approach that makes applications independent of the memory model of the hardware, hence they can be compiled to hardware with any memory architecture. The key is having a memory model that only guarantees the most fundamental orderings of reads and writes, and annotations to specify additional ordering constraints. As a result, tooling can transparently and properly implement fences, cache flushes, etc. when appropriate, without losing flexibility of the hardware design. In a case study, several SPLASH-2 applications are run on a 32-core software cache coherent MicroBlaze system in FPGA. Moreover, this approach also allows mapping to scratch-pad memories and a distributed shared memory architecture.
KW - EWI-23363
KW - IR-86199
KW - METIS-297648
KW - CAES-EEA: Efficient Embedded Architectures
U2 - 10.1109/IPDPSW.2013.14
DO - 10.1109/IPDPSW.2013.14
M3 - Conference contribution
SN - 978-0-7695-4979-8
SP - 212
EP - 221
BT - Proceedings of the 27th IEEE International Parallel and Distributed Processing Symposium (IPDPS 2013) - 20th Reconfigurable Architectures Workshop (RAW 2013)
PB - IEEE Computer Society
CY - USA
ER -