Power analysis on smartcard algorithms using simulation

G. Hollestelle, W. Burgers, Jeremy den Hartog

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    This paper presents the results from a power analysis of the AES and RSA algorithms by simulation using the PINPAS tool. The PINPAS tool is capable of simulating the power consumption of assembler programs implemented in, amongst others, Hitachi H8/300 assembler. The Hitachi H8/300 is a popular CPU for smartcards. Using the PINPAS tool, the vulnerability for power analysis attacks of straightforward AES and RSA implementations is examined. In case a vulnerability is found countermeasures are added to the implementation that attempt to counter power analysis attacks. After these modifications the analysis is performed again and the new results are compared to the original results.
    Original languageUndefined
    Place of PublicationEindhoven
    PublisherEindhoven University of Technology
    Publication statusPublished - 2004

    Publication series

    PublisherEindhoven University of Technology


    • METIS-222218
    • IR-66569
    • EWI-798

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