Abstract
The additional power dissipation involved in introducing a high dependability in multi-processor systems is nowadays becoming a major concern (power-aware dependability). In this paper, the power dissipation components of a recently implemented scan-test based dependability testing approach for a multi-processor Systems-on-Chip (SoC) is evaluated. It is shown that the application of scan-test vectors to the cores is the major power contributor. To avoid this dissipation and hence scan test, a new prognostic approach for life-time prediction using on-line health monitors is proposed accomplishing the same high dependability. It will be shown that the latter approach consumes less power under the same dependability specifications. Actual measurements and theoretical calculations are provided as well as a suggestion for future dependable systems given.
Original language | English |
---|---|
Title of host publication | 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) |
Editors | Yong Zhao |
Place of Publication | Piscataway, NJ |
Publisher | IEEE |
Pages | 56-61 |
Number of pages | 6 |
ISBN (Electronic) | 978-1-4673-6040-1, 978-1-4673-6038-8 |
ISBN (Print) | 978-1-4673-6039-5 |
DOIs | |
Publication status | Published - 26 Mar 2013 |
Event | 8th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era, DTIS 2013 - Abu Dhabi, United Arab Emirates Duration: 26 Mar 2013 → 28 Mar 2013 Conference number: 8 |
Conference
Conference | 8th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era, DTIS 2013 |
---|---|
Abbreviated title | DTIS |
Country/Territory | United Arab Emirates |
City | Abu Dhabi |
Period | 26/03/13 → 28/03/13 |
Keywords
- on-line health-monitoring
- dependability testing
- power-aware dependability
- MP-SoC systems
- prognostics