Abstract
Abstract—This paper presents a set of circuit techniques to
achieve high data rate point-to-point communication over long on-chip RC-limited wire-pairs. The ideal line termination impedances for a flat transfer function with linear phase (pure delay) are derived, using an s-parameter wire-pair model. It is shown that a driver with series capacitance on the one hand and a resistive load on the other, are fair approximations of these ideal terminations in the frequency range of interest. From a perspective of power efficiency, a capacitive driver is preferred,
as the series capacitance reduces the voltage swing along the line which reduces dynamic power consumption. To reduce cross-talk and maintain data integrity, parallel differential interconnects with alternatingly one or two twists are used. In combination with a low offset dynamic sense amplifier at the receiver, and a low-power decision feedback equalization technique with analog feedback, gigabit communication is demonstrated at very low
power consumption. A point-to-point link on a 90 nm CMOS
test chip achieves 2 Gb/s over 10 mm long interconnects, while consuming 0.28 pJ/bit corresponding to 28 fJ/bit/mm, which is much lower than competing designs.
Original language | English |
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Pages (from-to) | 447-457 |
Number of pages | 11 |
Journal | IEEE journal of solid-state circuits |
Volume | 45 |
Issue number | 2 |
DOIs | |
Publication status | Published - 1 Feb 2010 |
Keywords
- networks on chip
- on-chip interconnects
- on-chip wires
- communication techniques
- low power electronics
- low-swing
- de-emphasis
- decision feedback equalization
- pre-emphasis
- EWI-18144
- Equalization
- RC-limited interconnects
- NoC
- METIS-270913
- IR-73655
- Capacitive coupling
- CMOS