Power signature watermarking of IP cores for FPGAs

Daniel Ziener, Jürgen Teich

Research output: Contribution to journalArticleAcademicpeer-review

50 Citations (Scopus)

Abstract

In this paper, we introduce a new method for watermarking of IP cores for FPGA architectures where the signature (watermark) is detected at the power supply pins of the FPGA. This is the first watermarking method where the signature is extracted in this way. We are able to sign IP cores at the netlist as well as the bitfile level, so a wide spectrum of cores can be protected. In principle, the proposed power watermarking method works for all kinds of FPGAs. For Xilinx FPGAs, we demonstrate in detail that we can integrate the watermarking algorithms and the signature into the functionality of the watermarked core. So it is very hard to remove the watermark without destroying the core. Furthermore, we introduce a detection algorithm which can decode the signature from a voltage trace with high reliability. Additionally, two enhanced robustness algorithms are introduced which improve the detection probability in case of considerable noise sources. Using these techniques, it is possible to decode the signature even if other cores operate on the same device at the same time.

Original languageEnglish
Pages (from-to)123-136
Number of pages14
JournalJournal of signal processing systems for signal image and video technology
Volume51
Issue number1
DOIs
Publication statusPublished - Apr 2008
Externally publishedYes

Fingerprint

Watermarking
Field Programmable Gate Array
Field programmable gate arrays (FPGA)
Signature
Decode
Watermark
Detection Probability
Voltage
Integrate
Trace
Intellectual property core
Robustness
Electric potential
Demonstrate

Keywords

  • FPGA
  • IP cores
  • IPP
  • Power analysis
  • Signature
  • Watermarking

Cite this

@article{0f89e6190b5241f49e5d8b4040c8e674,
title = "Power signature watermarking of IP cores for FPGAs",
abstract = "In this paper, we introduce a new method for watermarking of IP cores for FPGA architectures where the signature (watermark) is detected at the power supply pins of the FPGA. This is the first watermarking method where the signature is extracted in this way. We are able to sign IP cores at the netlist as well as the bitfile level, so a wide spectrum of cores can be protected. In principle, the proposed power watermarking method works for all kinds of FPGAs. For Xilinx FPGAs, we demonstrate in detail that we can integrate the watermarking algorithms and the signature into the functionality of the watermarked core. So it is very hard to remove the watermark without destroying the core. Furthermore, we introduce a detection algorithm which can decode the signature from a voltage trace with high reliability. Additionally, two enhanced robustness algorithms are introduced which improve the detection probability in case of considerable noise sources. Using these techniques, it is possible to decode the signature even if other cores operate on the same device at the same time.",
keywords = "FPGA, IP cores, IPP, Power analysis, Signature, Watermarking",
author = "Daniel Ziener and J{\"u}rgen Teich",
year = "2008",
month = "4",
doi = "10.1007/s11265-007-0136-8",
language = "English",
volume = "51",
pages = "123--136",
journal = "Journal of signal processing systems for signal image and video technology",
issn = "1939-8018",
publisher = "Springer",
number = "1",

}

Power signature watermarking of IP cores for FPGAs. / Ziener, Daniel; Teich, Jürgen.

In: Journal of signal processing systems for signal image and video technology, Vol. 51, No. 1, 04.2008, p. 123-136.

Research output: Contribution to journalArticleAcademicpeer-review

TY - JOUR

T1 - Power signature watermarking of IP cores for FPGAs

AU - Ziener, Daniel

AU - Teich, Jürgen

PY - 2008/4

Y1 - 2008/4

N2 - In this paper, we introduce a new method for watermarking of IP cores for FPGA architectures where the signature (watermark) is detected at the power supply pins of the FPGA. This is the first watermarking method where the signature is extracted in this way. We are able to sign IP cores at the netlist as well as the bitfile level, so a wide spectrum of cores can be protected. In principle, the proposed power watermarking method works for all kinds of FPGAs. For Xilinx FPGAs, we demonstrate in detail that we can integrate the watermarking algorithms and the signature into the functionality of the watermarked core. So it is very hard to remove the watermark without destroying the core. Furthermore, we introduce a detection algorithm which can decode the signature from a voltage trace with high reliability. Additionally, two enhanced robustness algorithms are introduced which improve the detection probability in case of considerable noise sources. Using these techniques, it is possible to decode the signature even if other cores operate on the same device at the same time.

AB - In this paper, we introduce a new method for watermarking of IP cores for FPGA architectures where the signature (watermark) is detected at the power supply pins of the FPGA. This is the first watermarking method where the signature is extracted in this way. We are able to sign IP cores at the netlist as well as the bitfile level, so a wide spectrum of cores can be protected. In principle, the proposed power watermarking method works for all kinds of FPGAs. For Xilinx FPGAs, we demonstrate in detail that we can integrate the watermarking algorithms and the signature into the functionality of the watermarked core. So it is very hard to remove the watermark without destroying the core. Furthermore, we introduce a detection algorithm which can decode the signature from a voltage trace with high reliability. Additionally, two enhanced robustness algorithms are introduced which improve the detection probability in case of considerable noise sources. Using these techniques, it is possible to decode the signature even if other cores operate on the same device at the same time.

KW - FPGA

KW - IP cores

KW - IPP

KW - Power analysis

KW - Signature

KW - Watermarking

UR - http://www.scopus.com/inward/record.url?scp=43449102491&partnerID=8YFLogxK

U2 - 10.1007/s11265-007-0136-8

DO - 10.1007/s11265-007-0136-8

M3 - Article

VL - 51

SP - 123

EP - 136

JO - Journal of signal processing systems for signal image and video technology

JF - Journal of signal processing systems for signal image and video technology

SN - 1939-8018

IS - 1

ER -