Processes with 'incomplete' sensitivity lists and their synthesis aspects

Egbert Molenkamp, Gerhard E. Mekenkamp

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    Abstract

    Synthesis tools only support a subset of VHDL. In this paper, we focus on the synthesis aspects of processes with an incomplete sensitivity list. In general, processes with a sensitivity list are used to describe combinational logic and clocked logic. The sensitivity list is called `complete' when all signals which are read from within that process are in the sensitivity list, otherwise it has an `incomplete' sensitivity list. Most, if not all, synthesis tools require that the processes used to describe combinational logic should have a `complete' sensitivity list, while for synchronous logic only the reset, if any, and clock signals should be in the sensitivity list. Beside these two applications of processes with sensitivity lists, there is a vague support for other incomplete sensitivity lists, sometimes resulting in latches in the circuit and sometimes resulting in logic that does not have the proper behaviour. This paper focuses on the synthesis aspects of processes with an incomplete sensitivity list, and presents a method to synthesise a subset of these processes. Also, the problem of synthesising processes with an incomplete sensitivity list is discussed
    Original languageEnglish
    Title of host publicationRapid Systems Prototyping with VHDL
    Place of PublicationPiscataway, NJ
    PublisherIEEE
    Pages75-81
    Number of pages7
    ISBN (Print)0-8186-8180-2
    DOIs
    Publication statusPublished - 7 Nov 1997
    EventVHDL International Users' Forum, VIUF Fall 1997 - Arlington, United States
    Duration: 19 Oct 199722 Oct 1997

    Other

    OtherVHDL International Users' Forum, VIUF Fall 1997
    Abbreviated titleVIUF
    CountryUnited States
    CityArlington
    Period19/10/9722/10/97

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  • Cite this

    Molenkamp, E., & Mekenkamp, G. E. (1997). Processes with 'incomplete' sensitivity lists and their synthesis aspects. In Rapid Systems Prototyping with VHDL (pp. 75-81). Piscataway, NJ: IEEE. https://doi.org/10.1109/VIUF.1997.623933