Abstract
Synthesis tools only support a subset of VHDL. In this paper, we focus on the synthesis aspects of processes with an incomplete sensitivity list. In general, processes with a sensitivity list are used to describe combinational logic and clocked logic. The sensitivity list is called `complete' when all signals which are read from within that process are in the sensitivity list, otherwise it has an `incomplete' sensitivity list. Most, if not all, synthesis tools require that the processes used to describe combinational logic should have a `complete' sensitivity list, while for synchronous logic only the reset, if any, and clock signals should be in the sensitivity list. Beside these two applications of processes with sensitivity lists, there is a vague support for other incomplete sensitivity lists, sometimes resulting in latches in the circuit and sometimes resulting in logic that does not have the proper behaviour. This paper focuses on the synthesis aspects of processes with an incomplete sensitivity list, and presents a method to synthesise a subset of these processes. Also, the problem of synthesising processes with an incomplete sensitivity list is discussed
Original language | English |
---|---|
Title of host publication | Rapid Systems Prototyping with VHDL |
Place of Publication | Piscataway, NJ |
Publisher | IEEE |
Pages | 75-81 |
Number of pages | 7 |
ISBN (Print) | 0-8186-8180-2 |
DOIs | |
Publication status | Published - 7 Nov 1997 |
Event | VHDL International Users' Forum, VIUF Fall 1997 - Arlington, United States Duration: 19 Oct 1997 → 22 Oct 1997 |
Other
Other | VHDL International Users' Forum, VIUF Fall 1997 |
---|---|
Abbreviated title | VIUF |
Country/Territory | United States |
City | Arlington |
Period | 19/10/97 → 22/10/97 |