In this paper we present the study of gate-stress induced degradation in a-Si:H/SiN TFTs. The drain current transient during gate bias stress (forward or reverse bias) and subsequent relaxation cannot be fitted with the models existent in the literature but it shows to be described by a progressive degradation model (PDM). According to PDM the degradation of the electrical response is a combined effect of a fast interface traps generation and a slow charge trapping at the created defect sites and existing bulk defects in a-SiN:H transitional region.
|Number of pages||7|
|Journal||Thin solid films|
|Publication status||Published - 3 Mar 2003|
|Event||Symposium K on Thin Film Materials for Large Area Electronics 2002 - Strasbourg, France|
Duration: 3 Mar 2003 → 3 Mar 2003