Propagation of Delay in Probabilistic CMOS Systems

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Abstract

Future low voltage noise dominated designs render probabilistic behavior of CMOS. This is acceptable as far as applications’ intrinsic error resilience allows quantified inaccuracy in results to save energy consumption, such as in applications like audio/video processing and sky image formation in radio astronomy. This introduces the trade-off between energy consumption (E) and probability of correctness (p) that provides an opportunity for inexact computing to attain higher energy efficiency. Efforts have been made in the last decade to model probabilistic CMOS (PCMOS) keeping in view the noise variance and to establish its feasibility for error resilient applications focused on the nominal voltage range. However, exploiting the near threshold voltage (NTV) range is quite a promising energy efficient design technique that operates the hardware at relatively slower pace while retaining the deterministic property of computations. We propose to take the advantage of energy efficiency at NTV while retaining the speed as constant, sacrificing p to the extent allowed by applications resilience. In this regard, we investigated the impact of NTV operation on PCMOS where more energy can be saved with less accurate results. Our simulation results of an inverter and a 4-bit ripple carry adder in Cadence showed the shortcomings of current analytical models for probability of correctness at NTV and lower voltage supplies. We further investigated the impact of delay propagation in a digital system composed of probabilistic building blocks, which provides a clear insight of timing delay affecting the higher significant computational bits more than its lower significant counterparts and hence contributing considerably to the total error.
Original languageEnglish
Title of host publicationICT OPEN Proceedings 2017
Place of PublicationNetherlands
Pages23-26
Number of pages4
Publication statusPublished - 22 Mar 2017
EventICT.OPEN 2017 - The Flint, Amersfoort, Netherlands
Duration: 21 Mar 201722 Mar 2017

Conference

ConferenceICT.OPEN 2017
CountryNetherlands
CityAmersfoort
Period21/03/1722/03/17

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Threshold voltage
Energy efficiency
Electric potential
Energy utilization
Radio astronomy
Adders
Analytical models
Image processing
Hardware
Processing

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Oudshoorn, L., Gillani, G. A., & Kokkeler, A. B. J. (2017). Propagation of Delay in Probabilistic CMOS Systems. In ICT OPEN Proceedings 2017 (pp. 23-26). Netherlands.
Oudshoorn, L. ; Gillani, G.A. ; Kokkeler, Andre B.J. / Propagation of Delay in Probabilistic CMOS Systems. ICT OPEN Proceedings 2017. Netherlands, 2017. pp. 23-26
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Oudshoorn, L, Gillani, GA & Kokkeler, ABJ 2017, Propagation of Delay in Probabilistic CMOS Systems. in ICT OPEN Proceedings 2017. Netherlands, pp. 23-26, ICT.OPEN 2017, Amersfoort, Netherlands, 21/03/17.

Propagation of Delay in Probabilistic CMOS Systems. / Oudshoorn, L.; Gillani, G.A.; Kokkeler, Andre B.J.

ICT OPEN Proceedings 2017. Netherlands, 2017. p. 23-26.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademic

TY - GEN

T1 - Propagation of Delay in Probabilistic CMOS Systems

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N2 - Future low voltage noise dominated designs render probabilistic behavior of CMOS. This is acceptable as far as applications’ intrinsic error resilience allows quantified inaccuracy in results to save energy consumption, such as in applications like audio/video processing and sky image formation in radio astronomy. This introduces the trade-off between energy consumption (E) and probability of correctness (p) that provides an opportunity for inexact computing to attain higher energy efficiency. Efforts have been made in the last decade to model probabilistic CMOS (PCMOS) keeping in view the noise variance and to establish its feasibility for error resilient applications focused on the nominal voltage range. However, exploiting the near threshold voltage (NTV) range is quite a promising energy efficient design technique that operates the hardware at relatively slower pace while retaining the deterministic property of computations. We propose to take the advantage of energy efficiency at NTV while retaining the speed as constant, sacrificing p to the extent allowed by applications resilience. In this regard, we investigated the impact of NTV operation on PCMOS where more energy can be saved with less accurate results. Our simulation results of an inverter and a 4-bit ripple carry adder in Cadence showed the shortcomings of current analytical models for probability of correctness at NTV and lower voltage supplies. We further investigated the impact of delay propagation in a digital system composed of probabilistic building blocks, which provides a clear insight of timing delay affecting the higher significant computational bits more than its lower significant counterparts and hence contributing considerably to the total error.

AB - Future low voltage noise dominated designs render probabilistic behavior of CMOS. This is acceptable as far as applications’ intrinsic error resilience allows quantified inaccuracy in results to save energy consumption, such as in applications like audio/video processing and sky image formation in radio astronomy. This introduces the trade-off between energy consumption (E) and probability of correctness (p) that provides an opportunity for inexact computing to attain higher energy efficiency. Efforts have been made in the last decade to model probabilistic CMOS (PCMOS) keeping in view the noise variance and to establish its feasibility for error resilient applications focused on the nominal voltage range. However, exploiting the near threshold voltage (NTV) range is quite a promising energy efficient design technique that operates the hardware at relatively slower pace while retaining the deterministic property of computations. We propose to take the advantage of energy efficiency at NTV while retaining the speed as constant, sacrificing p to the extent allowed by applications resilience. In this regard, we investigated the impact of NTV operation on PCMOS where more energy can be saved with less accurate results. Our simulation results of an inverter and a 4-bit ripple carry adder in Cadence showed the shortcomings of current analytical models for probability of correctness at NTV and lower voltage supplies. We further investigated the impact of delay propagation in a digital system composed of probabilistic building blocks, which provides a clear insight of timing delay affecting the higher significant computational bits more than its lower significant counterparts and hence contributing considerably to the total error.

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Oudshoorn L, Gillani GA, Kokkeler ABJ. Propagation of Delay in Probabilistic CMOS Systems. In ICT OPEN Proceedings 2017. Netherlands. 2017. p. 23-26