Range pre-selection sampling technique to reduce input drive energy for SAR ADCs

Harijot Singh Bindra; Joeri Boris Lechevallier; Anne Johan Annema; S.M. Louwsma; Adrianus Johannes Maria van Tuijl; Bram  Nauta

doi:10.1109/ASSCC.2017.8240255

Range pre-selection sampling technique to reduce input drive energy for SAR ADCs

Harijot Singh Bindra, Joeri Boris Lechevallier, Anne Johan Annema, S.M. Louwsma, Adrianus Johannes Maria van Tuijl, Bram Nauta

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

8 Citations (Scopus)

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Abstract

A Range Pre-selection Sampling (RPS) technique is introduced to reduce the input drive energy for SAR ADCs and is applied to a 10-bit 2MS/s SAR ADC in 65nm CMOS in this paper. Using the proposed RPS technique, the peak input sampling current and hence the input drive power requirement is reduced by a factor 2.4 as compared to conventional sampling (CS). Considering an ideal Class A operation for the buffer circuit driving the ADC, this translates into a minimum (theoretical) driver power consumption of 50μW for our RPS based ADC whereas it is 130μW for the conventional sampling, both much larger than the ADC power consumption of 3.25μW at 1MS/s operation. Our ADC occupies an area of 0.08 mm2and achieves an SFDR of 64 dB, an SNDR of 55 dB with a Walden Figure of Merit, FoMw of 6.8fJ/conversion-step at up-to 2MS/s.

Original language	English
Title of host publication	IEEE Asian Solid-State Circuits Conference (A-SSCC)
Subtitle of host publication	proceedings of technical papers
Place of Publication	Piscataway, NJ
Publisher	IEEE
Pages	217-220
Number of pages	4
ISBN (Electronic)	978-1-5386-3178-2
ISBN (Print)	978-1-5386-3179-9
DOIs	https://doi.org/10.1109/ASSCC.2017.8240255
Publication status	Published - 8 Nov 2017
Event	IEEE Asian Solid-State Circuits Conference, A-SSCC 2017 - Grand Hilton Hotel, Seoul, Korea, Republic of Duration: 6 Nov 2017 → 8 Nov 2017

Conference

Conference	IEEE Asian Solid-State Circuits Conference, A-SSCC 2017
Abbreviated title	A-SSCC
Country/Territory	Korea, Republic of
City	Seoul
Period	6/11/17 → 8/11/17

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10.1109/ASSCC.2017.8240255

Bindra ASSCAccepted author version, 963 KB

Cite this

@inproceedings{e23bcd0191e94ae1b39db51b78eef108,

title = "Range pre-selection sampling technique to reduce input drive energy for SAR ADCs",

abstract = "A Range Pre-selection Sampling (RPS) technique is introduced to reduce the input drive energy for SAR ADCs and is applied to a 10-bit 2MS/s SAR ADC in 65nm CMOS in this paper. Using the proposed RPS technique, the peak input sampling current and hence the input drive power requirement is reduced by a factor 2.4 as compared to conventional sampling (CS). Considering an ideal Class A operation for the buffer circuit driving the ADC, this translates into a minimum (theoretical) driver power consumption of 50μW for our RPS based ADC whereas it is 130μW for the conventional sampling, both much larger than the ADC power consumption of 3.25μW at 1MS/s operation. Our ADC occupies an area of 0.08 mm2and achieves an SFDR of 64 dB, an SNDR of 55 dB with a Walden Figure of Merit, FoMw of 6.8fJ/conversion-step at up-to 2MS/s. ",

author = "Bindra, {Harijot Singh} and Lechevallier, {Joeri Boris} and Annema, {Anne Johan} and S.M. Louwsma and {van Tuijl}, {Adrianus Johannes Maria} and Bram Nauta",

year = "2017",

month = nov,

day = "8",

doi = "10.1109/ASSCC.2017.8240255",

language = "English",

isbn = "978-1-5386-3179-9 ",

pages = "217--220",

booktitle = "IEEE Asian Solid-State Circuits Conference (A-SSCC)",

publisher = "IEEE",

address = "United States",

note = "IEEE Asian Solid-State Circuits Conference, A-SSCC 2017, A-SSCC ; Conference date: 06-11-2017 Through 08-11-2017",

}

Bindra, HS, Lechevallier, JB, Annema, AJ, Louwsma, SM, van Tuijl, AJM & Nauta, B 2017, Range pre-selection sampling technique to reduce input drive energy for SAR ADCs. in IEEE Asian Solid-State Circuits Conference (A-SSCC): proceedings of technical papers. IEEE, Piscataway, NJ, pp. 217-220, IEEE Asian Solid-State Circuits Conference, A-SSCC 2017, Seoul, Korea, Republic of, 6/11/17. https://doi.org/10.1109/ASSCC.2017.8240255

Range pre-selection sampling technique to reduce input drive energy for SAR ADCs. / Bindra, Harijot Singh; Lechevallier, Joeri Boris; Annema, Anne Johan et al.
IEEE Asian Solid-State Circuits Conference (A-SSCC): proceedings of technical papers. Piscataway, NJ: IEEE, 2017. p. 217-220.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Range pre-selection sampling technique to reduce input drive energy for SAR ADCs

AU - Bindra, Harijot Singh

AU - Lechevallier, Joeri Boris

AU - Annema, Anne Johan

AU - Louwsma, S.M.

AU - van Tuijl, Adrianus Johannes Maria

AU - Nauta, Bram

PY - 2017/11/8

Y1 - 2017/11/8

N2 - A Range Pre-selection Sampling (RPS) technique is introduced to reduce the input drive energy for SAR ADCs and is applied to a 10-bit 2MS/s SAR ADC in 65nm CMOS in this paper. Using the proposed RPS technique, the peak input sampling current and hence the input drive power requirement is reduced by a factor 2.4 as compared to conventional sampling (CS). Considering an ideal Class A operation for the buffer circuit driving the ADC, this translates into a minimum (theoretical) driver power consumption of 50μW for our RPS based ADC whereas it is 130μW for the conventional sampling, both much larger than the ADC power consumption of 3.25μW at 1MS/s operation. Our ADC occupies an area of 0.08 mm2and achieves an SFDR of 64 dB, an SNDR of 55 dB with a Walden Figure of Merit, FoMw of 6.8fJ/conversion-step at up-to 2MS/s.

AB - A Range Pre-selection Sampling (RPS) technique is introduced to reduce the input drive energy for SAR ADCs and is applied to a 10-bit 2MS/s SAR ADC in 65nm CMOS in this paper. Using the proposed RPS technique, the peak input sampling current and hence the input drive power requirement is reduced by a factor 2.4 as compared to conventional sampling (CS). Considering an ideal Class A operation for the buffer circuit driving the ADC, this translates into a minimum (theoretical) driver power consumption of 50μW for our RPS based ADC whereas it is 130μW for the conventional sampling, both much larger than the ADC power consumption of 3.25μW at 1MS/s operation. Our ADC occupies an area of 0.08 mm2and achieves an SFDR of 64 dB, an SNDR of 55 dB with a Walden Figure of Merit, FoMw of 6.8fJ/conversion-step at up-to 2MS/s.

UR - https://ieeexplore.ieee.org/document/8240255/

U2 - 10.1109/ASSCC.2017.8240255

DO - 10.1109/ASSCC.2017.8240255

M3 - Conference contribution

SN - 978-1-5386-3179-9

SP - 217

EP - 220

BT - IEEE Asian Solid-State Circuits Conference (A-SSCC)

PB - IEEE

CY - Piscataway, NJ

T2 - IEEE Asian Solid-State Circuits Conference, A-SSCC 2017

Y2 - 6 November 2017 through 8 November 2017

ER -

Range pre-selection sampling technique to reduce input drive energy for SAR ADCs

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A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply

Low Energy Design Techniques For Data Converters

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