Real-time multiprocessor architecture for sharing stream processing accelerators

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Abstract

Stream processing accelerators are often applied in MPSoCs for software defined radios. Sharing of these accelerators between different streams could improve their utilization and reduce thereby the hardware cost but is challenging under real-time constraints. In this paper we introduce entry- and exit-gateways that are responsible for multiplexing blocks of data over accelerators under real-time constraints. These gateways check for the availability of sufficient data and space and thereby enable the derivation of a dataflow model of the application. The dataflow model is used to verify the worst-case temporal behavior based on the sizes of the blocks of data used for multiplexing. We demonstrate that required buffer capacities are non-monotone in the block size. Therefore, an ILP is presented to compute minimum block sizes and sufficient buffer capacities. The benefits of sharing accelerators are demonstrated using a multi-core system that is implemented on a Virtex 6 FPGA. A stereo audio stream from a PAL video signal is demodulated in this system in real-time where two accelerators are shared within and between two streams. In this system sharing reduces the number of accelerators by 75% and reduced the number of logic cells with 63%.
Original languageUndefined
Title of host publication22nd Reconfigurable Architectures Workshop (RAW 2015)
Place of PublicationUSA
PublisherIEEE Computer Society
Pages81-89
Number of pages9
ISBN (Print)978-1-4673-7684-6
DOIs
Publication statusPublished - 25 May 2015

Publication series

Name
PublisherIEEE Computer Society

Keywords

  • Real-time applications
  • multiprocessing systems
  • stream processing accelerators
  • METIS-312627
  • IR-96052
  • Data flow
  • accelerator sharing
  • EWI-26067

Cite this

Dekens, B. H. J., Bekooij, M. J. G., & Smit, G. J. M. (2015). Real-time multiprocessor architecture for sharing stream processing accelerators. In 22nd Reconfigurable Architectures Workshop (RAW 2015) (pp. 81-89). USA: IEEE Computer Society. https://doi.org/10.1109/IPDPSW.2015.147
Dekens, B.H.J. ; Bekooij, Marco Jan Gerrit ; Smit, Gerardus Johannes Maria. / Real-time multiprocessor architecture for sharing stream processing accelerators. 22nd Reconfigurable Architectures Workshop (RAW 2015). USA : IEEE Computer Society, 2015. pp. 81-89
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Dekens, BHJ, Bekooij, MJG & Smit, GJM 2015, Real-time multiprocessor architecture for sharing stream processing accelerators. in 22nd Reconfigurable Architectures Workshop (RAW 2015). IEEE Computer Society, USA, pp. 81-89. https://doi.org/10.1109/IPDPSW.2015.147

Real-time multiprocessor architecture for sharing stream processing accelerators. / Dekens, B.H.J.; Bekooij, Marco Jan Gerrit; Smit, Gerardus Johannes Maria.

22nd Reconfigurable Architectures Workshop (RAW 2015). USA : IEEE Computer Society, 2015. p. 81-89.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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N2 - Stream processing accelerators are often applied in MPSoCs for software defined radios. Sharing of these accelerators between different streams could improve their utilization and reduce thereby the hardware cost but is challenging under real-time constraints. In this paper we introduce entry- and exit-gateways that are responsible for multiplexing blocks of data over accelerators under real-time constraints. These gateways check for the availability of sufficient data and space and thereby enable the derivation of a dataflow model of the application. The dataflow model is used to verify the worst-case temporal behavior based on the sizes of the blocks of data used for multiplexing. We demonstrate that required buffer capacities are non-monotone in the block size. Therefore, an ILP is presented to compute minimum block sizes and sufficient buffer capacities. The benefits of sharing accelerators are demonstrated using a multi-core system that is implemented on a Virtex 6 FPGA. A stereo audio stream from a PAL video signal is demodulated in this system in real-time where two accelerators are shared within and between two streams. In this system sharing reduces the number of accelerators by 75% and reduced the number of logic cells with 63%.

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Dekens BHJ, Bekooij MJG, Smit GJM. Real-time multiprocessor architecture for sharing stream processing accelerators. In 22nd Reconfigurable Architectures Workshop (RAW 2015). USA: IEEE Computer Society. 2015. p. 81-89 https://doi.org/10.1109/IPDPSW.2015.147