Realisation of a 0.25 μm NMOSFET using GexSi1-x(x≪0.4) as Gate Material

C. Salm; J. Schmitz; M.C. Martens; D.J. Gravesteijn; J. Holleman; P.H. Woerlee

Realisation of a 0.25 μm NMOSFET using GexSi1-x(x≪0.4) as Gate Material

C. Salm^*
, J. Schmitz
, M.C. Martens
, D.J. Gravesteijn
, J. Holleman
, P.H. Woerlee

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

1 Citation (Scopus)

48 Downloads (Pure)

Abstract

The realisation a 0.25 μm NMOSFET using arsenic implanted Ge_xSi_1-xas gate material, with minimal changes in an existing process is reported. The etching of this gate material does not pose a problem and the underlying thin gate oxide is hardly attacked. We will show good transistor characteristics for both a 6nm and a 4.5 nm oxide thickness. V_Troll-off is comparable for the poly-Si and poly-Ge_xSi_1-xgates.

Original language	English
Title of host publication	ESSDERC 1996
Subtitle of host publication	Proceedings of the 26th European Solid State Device Research Conference
Editors	Massimo Rudan, Giorgio Baccarani
Place of Publication	Piscataway, NJ
Publisher	IEEE
Pages	601-604
Number of pages	4
ISBN (Print)	9782863321966
Publication status	Published - 1 Jan 1996
Event	26th European Solid State Device Research Conference, ESSDERC 1996 - Bologna, Italy Duration: 9 Sept 1996 → 11 Sept 1996 Conference number: 26

Conference

Conference	26th European Solid State Device Research Conference, ESSDERC 1996
Abbreviated title	ESSDERC
Country/Territory	Italy
City	Bologna
Period	9/09/96 → 11/09/96

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Salm, C., Schmitz, J., Martens, M. C., Gravesteijn, D. J., Holleman, J., & Woerlee, P. H. (1996). Realisation of a 0.25 μm NMOSFET using GexSi1-x(x≪0.4) as Gate Material. In M. Rudan, & G. Baccarani (Eds.), ESSDERC 1996: Proceedings of the 26th European Solid State Device Research Conference (pp. 601-604). Article 5436139 IEEE. https://ieeexplore.ieee.org/document/5436139

@inproceedings{522f67c89b454e91b50fdb599c1f9740,

title = "Realisation of a 0.25 μm NMOSFET using GexSi1-x(x≪0.4) as Gate Material",

abstract = "The realisation a 0.25 μm NMOSFET using arsenic implanted GexSi1-xas gate material, with minimal changes in an existing process is reported. The etching of this gate material does not pose a problem and the underlying thin gate oxide is hardly attacked. We will show good transistor characteristics for both a 6nm and a 4.5 nm oxide thickness. VTroll-off is comparable for the poly-Si and poly-GexSi1-xgates.",

author = "C. Salm and J. Schmitz and M.C. Martens and D.J. Gravesteijn and J. Holleman and P.H. Woerlee",

year = "1996",

month = jan,

day = "1",

language = "English",

isbn = "9782863321966",

pages = "601--604",

editor = "Massimo Rudan and Giorgio Baccarani",

booktitle = "ESSDERC 1996",

publisher = "IEEE",

address = "United States",

note = "26th European Solid State Device Research Conference, ESSDERC 1996, ESSDERC ; Conference date: 09-09-1996 Through 11-09-1996",

}

Salm, C , Schmitz, J, Martens, MC, Gravesteijn, DJ, Holleman, J & Woerlee, PH 1996, Realisation of a 0.25 μm NMOSFET using GexSi1-x(x≪0.4) as Gate Material. in M Rudan & G Baccarani (eds), ESSDERC 1996: Proceedings of the 26th European Solid State Device Research Conference., 5436139, IEEE, Piscataway, NJ, pp. 601-604, 26th European Solid State Device Research Conference, ESSDERC 1996, Bologna, Italy, 9/09/96. <https://ieeexplore.ieee.org/document/5436139>

Realisation of a 0.25 μm NMOSFET using GexSi1-x(x≪0.4) as Gate Material. / Salm, C.; Schmitz, J.; Martens, M.C. et al.
ESSDERC 1996: Proceedings of the 26th European Solid State Device Research Conference. ed. / Massimo Rudan; Giorgio Baccarani. Piscataway, NJ: IEEE, 1996. p. 601-604 5436139.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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T1 - Realisation of a 0.25 μm NMOSFET using GexSi1-x(x≪0.4) as Gate Material

AU - Salm, C.

AU - Schmitz, J.

AU - Martens, M.C.

AU - Gravesteijn, D.J.

AU - Holleman, J.

AU - Woerlee, P.H.

N1 - Conference code: 26

PY - 1996/1/1

Y1 - 1996/1/1

N2 - The realisation a 0.25 μm NMOSFET using arsenic implanted GexSi1-xas gate material, with minimal changes in an existing process is reported. The etching of this gate material does not pose a problem and the underlying thin gate oxide is hardly attacked. We will show good transistor characteristics for both a 6nm and a 4.5 nm oxide thickness. VTroll-off is comparable for the poly-Si and poly-GexSi1-xgates.

AB - The realisation a 0.25 μm NMOSFET using arsenic implanted GexSi1-xas gate material, with minimal changes in an existing process is reported. The etching of this gate material does not pose a problem and the underlying thin gate oxide is hardly attacked. We will show good transistor characteristics for both a 6nm and a 4.5 nm oxide thickness. VTroll-off is comparable for the poly-Si and poly-GexSi1-xgates.

UR - https://www.scopus.com/pages/publications/84920728632

M3 - Conference contribution

AN - SCOPUS:84920728632

SN - 9782863321966

SP - 601

EP - 604

BT - ESSDERC 1996

A2 - Rudan, Massimo

A2 - Baccarani, Giorgio

PB - IEEE

CY - Piscataway, NJ

T2 - 26th European Solid State Device Research Conference, ESSDERC 1996

Y2 - 9 September 1996 through 11 September 1996

ER -

Realisation of a 0.25 μm NMOSFET using GexSi1-x(x≪0.4) as Gate Material

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