Reconfigurable Multicore Architectures for Streaming Applications

Gerardus Johannes Maria Smit, Andre B.J. Kokkeler, G.K. Rauwerda, J.W.M. Jacobs

    Research output: Chapter in Book/Report/Conference proceedingChapterAcademicpeer-review

    Abstract

    This chapter addresses reconfigurable heterogenous and homogeneous multicore system-on-chip (SoC) platforms for streaming digital signal processing applications, also called DSP applications. In streaming DSP applications, computations can be specified as a data flow graph with streams of data items (the edges) flowing between computation kernels (the nodes). Most signal processing applications can be naturally expressed in this modeling style. Typical examples of streaming DSP applications are wireless baseband processing, multimedia processing, medical image processing, sensor processing (e.g., for remote surveillance cameras), and phased array radars. In a heterogeneous multicore architecture, a core can either be a bitlevel reconfigurable unit (e.g., FPGA), a word-level reconfigurable unit, or a general-purpose programmable unit (digital signal processor (DSP) or general purpose processor (GPP)). We assume the cores of the SoC are interconnected by a reconfigurable network-on-chip (NoC). The programmability of the individual cores enables the system to be targeted at multiple application domains. We take a holistic approach, which means that all aspects of systems design need to be addressed simultaneously in a systematic way. This is key for an efficient overall solution, because an interesting optimization in a small corner of the design might lead to inefficiencies in the overall design. We introduce streaming applications and multi-core architectures We present key design criteria for streaming applications and give a multi-dimensional classification of architectures for streaming applications. For each category one or more sample architectures are presented.
    Original languageUndefined
    Title of host publicationModel-Based Desing for Embedded Systems
    EditorsG. Nicolescu, P.J. Mosterman
    Place of PublicationBoca Raton, Florida
    PublisherCRC Press
    Pages323-350
    Number of pages28
    ISBN (Print)978-1-4200678-4-2
    Publication statusPublished - 23 Nov 2009

    Publication series

    Name
    PublisherCRC Press

    Keywords

    • METIS-268946
    • IR-72178
    • Reconfigurable architectures
    • Streaming Applications
    • Network-on-Chip
    • EWI-18070
    • System on Chip
    • Embedded Systems

    Cite this

    Smit, G. J. M., Kokkeler, A. B. J., Rauwerda, G. K., & Jacobs, J. W. M. (2009). Reconfigurable Multicore Architectures for Streaming Applications. In G. Nicolescu, & P. J. Mosterman (Eds.), Model-Based Desing for Embedded Systems (pp. 323-350). Boca Raton, Florida: CRC Press.
    Smit, Gerardus Johannes Maria ; Kokkeler, Andre B.J. ; Rauwerda, G.K. ; Jacobs, J.W.M. / Reconfigurable Multicore Architectures for Streaming Applications. Model-Based Desing for Embedded Systems. editor / G. Nicolescu ; P.J. Mosterman. Boca Raton, Florida : CRC Press, 2009. pp. 323-350
    @inbook{ac56ad16c62b4b5e842e430e28b63419,
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    abstract = "This chapter addresses reconfigurable heterogenous and homogeneous multicore system-on-chip (SoC) platforms for streaming digital signal processing applications, also called DSP applications. In streaming DSP applications, computations can be specified as a data flow graph with streams of data items (the edges) flowing between computation kernels (the nodes). Most signal processing applications can be naturally expressed in this modeling style. Typical examples of streaming DSP applications are wireless baseband processing, multimedia processing, medical image processing, sensor processing (e.g., for remote surveillance cameras), and phased array radars. In a heterogeneous multicore architecture, a core can either be a bitlevel reconfigurable unit (e.g., FPGA), a word-level reconfigurable unit, or a general-purpose programmable unit (digital signal processor (DSP) or general purpose processor (GPP)). We assume the cores of the SoC are interconnected by a reconfigurable network-on-chip (NoC). The programmability of the individual cores enables the system to be targeted at multiple application domains. We take a holistic approach, which means that all aspects of systems design need to be addressed simultaneously in a systematic way. This is key for an efficient overall solution, because an interesting optimization in a small corner of the design might lead to inefficiencies in the overall design. We introduce streaming applications and multi-core architectures We present key design criteria for streaming applications and give a multi-dimensional classification of architectures for streaming applications. For each category one or more sample architectures are presented.",
    keywords = "METIS-268946, IR-72178, Reconfigurable architectures, Streaming Applications, Network-on-Chip, EWI-18070, System on Chip, Embedded Systems",
    author = "Smit, {Gerardus Johannes Maria} and Kokkeler, {Andre B.J.} and G.K. Rauwerda and J.W.M. Jacobs",
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    Smit, GJM, Kokkeler, ABJ, Rauwerda, GK & Jacobs, JWM 2009, Reconfigurable Multicore Architectures for Streaming Applications. in G Nicolescu & PJ Mosterman (eds), Model-Based Desing for Embedded Systems. CRC Press, Boca Raton, Florida, pp. 323-350.

    Reconfigurable Multicore Architectures for Streaming Applications. / Smit, Gerardus Johannes Maria; Kokkeler, Andre B.J.; Rauwerda, G.K.; Jacobs, J.W.M.

    Model-Based Desing for Embedded Systems. ed. / G. Nicolescu; P.J. Mosterman. Boca Raton, Florida : CRC Press, 2009. p. 323-350.

    Research output: Chapter in Book/Report/Conference proceedingChapterAcademicpeer-review

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    AU - Kokkeler, Andre B.J.

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    PY - 2009/11/23

    Y1 - 2009/11/23

    N2 - This chapter addresses reconfigurable heterogenous and homogeneous multicore system-on-chip (SoC) platforms for streaming digital signal processing applications, also called DSP applications. In streaming DSP applications, computations can be specified as a data flow graph with streams of data items (the edges) flowing between computation kernels (the nodes). Most signal processing applications can be naturally expressed in this modeling style. Typical examples of streaming DSP applications are wireless baseband processing, multimedia processing, medical image processing, sensor processing (e.g., for remote surveillance cameras), and phased array radars. In a heterogeneous multicore architecture, a core can either be a bitlevel reconfigurable unit (e.g., FPGA), a word-level reconfigurable unit, or a general-purpose programmable unit (digital signal processor (DSP) or general purpose processor (GPP)). We assume the cores of the SoC are interconnected by a reconfigurable network-on-chip (NoC). The programmability of the individual cores enables the system to be targeted at multiple application domains. We take a holistic approach, which means that all aspects of systems design need to be addressed simultaneously in a systematic way. This is key for an efficient overall solution, because an interesting optimization in a small corner of the design might lead to inefficiencies in the overall design. We introduce streaming applications and multi-core architectures We present key design criteria for streaming applications and give a multi-dimensional classification of architectures for streaming applications. For each category one or more sample architectures are presented.

    AB - This chapter addresses reconfigurable heterogenous and homogeneous multicore system-on-chip (SoC) platforms for streaming digital signal processing applications, also called DSP applications. In streaming DSP applications, computations can be specified as a data flow graph with streams of data items (the edges) flowing between computation kernels (the nodes). Most signal processing applications can be naturally expressed in this modeling style. Typical examples of streaming DSP applications are wireless baseband processing, multimedia processing, medical image processing, sensor processing (e.g., for remote surveillance cameras), and phased array radars. In a heterogeneous multicore architecture, a core can either be a bitlevel reconfigurable unit (e.g., FPGA), a word-level reconfigurable unit, or a general-purpose programmable unit (digital signal processor (DSP) or general purpose processor (GPP)). We assume the cores of the SoC are interconnected by a reconfigurable network-on-chip (NoC). The programmability of the individual cores enables the system to be targeted at multiple application domains. We take a holistic approach, which means that all aspects of systems design need to be addressed simultaneously in a systematic way. This is key for an efficient overall solution, because an interesting optimization in a small corner of the design might lead to inefficiencies in the overall design. We introduce streaming applications and multi-core architectures We present key design criteria for streaming applications and give a multi-dimensional classification of architectures for streaming applications. For each category one or more sample architectures are presented.

    KW - METIS-268946

    KW - IR-72178

    KW - Reconfigurable architectures

    KW - Streaming Applications

    KW - Network-on-Chip

    KW - EWI-18070

    KW - System on Chip

    KW - Embedded Systems

    M3 - Chapter

    SN - 978-1-4200678-4-2

    SP - 323

    EP - 350

    BT - Model-Based Desing for Embedded Systems

    A2 - Nicolescu, G.

    A2 - Mosterman, P.J.

    PB - CRC Press

    CY - Boca Raton, Florida

    ER -

    Smit GJM, Kokkeler ABJ, Rauwerda GK, Jacobs JWM. Reconfigurable Multicore Architectures for Streaming Applications. In Nicolescu G, Mosterman PJ, editors, Model-Based Desing for Embedded Systems. Boca Raton, Florida: CRC Press. 2009. p. 323-350