Abstract
A process is shown by which both the specific on-resistance R ds,on and the gate-drain charge density Qgd can be reduced. Reduction of the Rds,on is achieved by optimising the channel profile (p-body) towards a more box-shaped profile. The Qgd is reduced by going to smaller trench dimensions below the I-line lithography limits, without using deep-UV lithography. For polygonal cell structures, it is shown that narrowing the trenches also gives further Rds,on reduction. Record values for Rds,on of 4 mω·mm 2 (at Vgs = 10V) have been obtained for a 20V Trench MOSFET with a 2 μm cell pitch. Furthermore, for a 'conventional' 30V Trench MOSFET, we obtained an Rds,on of 7 mω·mm2 (at Vgs = 10V) by a more box-shaped p-body profile.
Original language | English |
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Title of host publication | ISPSD '03. 2003 IEEE 15th International Symposium on Power Semiconductor Devices and ICs, 2003. Proceedings. |
Publisher | IEEE |
Pages | 32-35 |
Number of pages | 4 |
ISBN (Print) | 0-7803-7876-8 |
DOIs | |
Publication status | Published - 1 Sept 2003 |
Externally published | Yes |
Event | 15th International Symposium on Power Semiconductor Devices and ICs 2003 - Cambridge, United Kingdom Duration: 14 Jul 2003 → 17 Jul 2003 Conference number: 15 |
Conference
Conference | 15th International Symposium on Power Semiconductor Devices and ICs 2003 |
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Abbreviated title | ISPSD 2003 |
Country/Territory | United Kingdom |
City | Cambridge |
Period | 14/07/03 → 17/07/03 |