A process is shown by which both the specific on-resistance Rds,on and the gate-drain charge density Qgd can be reduced. Reduction of Rds,on is achieved by optimising the channel profile (p-body) towards a more box-shaped profile. Qgd is reduced by reducing the gate-trench widths below the I-line lithography limits, without using deep-UV lithography. For polygonal cell structures, it is shown that trench width reduction also gives further Rds,on reduction. Record values for Rds,on of 4 mΩ · mm2 (at Vgs = 10 V) have been obtained for a 20 V trench MOSFET with a 2 μm cell pitch. Furthermore, for a 30 V trench MOSFET with a 2 μm cell pitch, an Rds,on of 7 mΩ · mm2 (at Vgs = 10 V) was obtained by using a more box-shaped p-body profile.
|Number of pages||4|
|Journal||IEE Proceedings: Circuits, Devices and Systems|
|Publication status||Published - 1 Jun 2004|
|Event||15th International Symposium on Power Semiconductor Devices and ICs 2003 - Cambridge, United Kingdom|
Duration: 14 Jul 2003 → 17 Jul 2003
Conference number: 15