Record low specific on-resistance for low-voltage trench MOSFETs

M. A.A. In't Zandt*, E. A. Hijzen, R. J.E. Hueting, G. E.J. Koops

*Corresponding author for this work

Research output: Contribution to journalConference articleAcademicpeer-review

4 Citations (Scopus)

Abstract

A process is shown by which both the specific on-resistance Rds,on and the gate-drain charge density Qgd can be reduced. Reduction of Rds,on is achieved by optimising the channel profile (p-body) towards a more box-shaped profile. Qgd is reduced by reducing the gate-trench widths below the I-line lithography limits, without using deep-UV lithography. For polygonal cell structures, it is shown that trench width reduction also gives further Rds,on reduction. Record values for Rds,on of 4 mΩ · mm2 (at Vgs = 10 V) have been obtained for a 20 V trench MOSFET with a 2 μm cell pitch. Furthermore, for a 30 V trench MOSFET with a 2 μm cell pitch, an Rds,on of 7 mΩ · mm2 (at Vgs = 10 V) was obtained by using a more box-shaped p-body profile.

Original languageEnglish
Pages (from-to)269-272
Number of pages4
JournalIEE Proceedings: Circuits, Devices and Systems
Volume151
Issue number3
DOIs
Publication statusPublished - 1 Jun 2004
Externally publishedYes
Event15th International Symposium on Power Semiconductor Devices and ICs 2003 - Cambridge, United Kingdom
Duration: 14 Jul 200317 Jul 2003
Conference number: 15

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