Record low specific on-resistance for low-voltage trench MOSFETs

M. A.A. In't Zandt; E. A. Hijzen; R. J.E. Hueting; G. E.J. Koops

doi:10.1049/ip-cds:20040444

Record low specific on-resistance for low-voltage trench MOSFETs

M. A.A. In't Zandt^*
, E. A. Hijzen
, R. J.E. Hueting
, G. E.J. Koops

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › Academic › peer-review

4 Citations (Scopus)

Abstract

A process is shown by which both the specific on-resistance R_ds,on and the gate-drain charge density Q_gd can be reduced. Reduction of R_ds,on is achieved by optimising the channel profile (p-body) towards a more box-shaped profile. Q_gd is reduced by reducing the gate-trench widths below the I-line lithography limits, without using deep-UV lithography. For polygonal cell structures, it is shown that trench width reduction also gives further R_ds,on reduction. Record values for R_ds,on of 4 mΩ · mm² (at V_gs = 10 V) have been obtained for a 20 V trench MOSFET with a 2 μm cell pitch. Furthermore, for a 30 V trench MOSFET with a 2 μm cell pitch, an R_ds,on of 7 mΩ · mm² (at V_gs = 10 V) was obtained by using a more box-shaped p-body profile.

Original language	English
Pages (from-to)	269-272
Number of pages	4
Journal	IEE Proceedings: Circuits, Devices and Systems
Volume	151
Issue number	3
DOIs	https://doi.org/10.1049/ip-cds:20040444
Publication status	Published - 1 Jun 2004
Externally published	Yes
Event	15th International Symposium on Power Semiconductor Devices and ICs 2003 - Cambridge, United Kingdom Duration: 14 Jul 2003 → 17 Jul 2003 Conference number: 15

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title = "Record low specific on-resistance for low-voltage trench MOSFETs",

abstract = "A process is shown by which both the specific on-resistance Rds,on and the gate-drain charge density Qgd can be reduced. Reduction of Rds,on is achieved by optimising the channel profile (p-body) towards a more box-shaped profile. Qgd is reduced by reducing the gate-trench widths below the I-line lithography limits, without using deep-UV lithography. For polygonal cell structures, it is shown that trench width reduction also gives further Rds,on reduction. Record values for Rds,on of 4 mΩ · mm2 (at Vgs = 10 V) have been obtained for a 20 V trench MOSFET with a 2 μm cell pitch. Furthermore, for a 30 V trench MOSFET with a 2 μm cell pitch, an Rds,on of 7 mΩ · mm2 (at Vgs = 10 V) was obtained by using a more box-shaped p-body profile.",

author = "\{In't Zandt\}, \{M. A.A.\} and Hijzen, \{E. A.\} and Hueting, \{R. J.E.\} and Koops, \{G. E.J.\}",

year = "2004",

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doi = "10.1049/ip-cds:20040444",

language = "English",

volume = "151",

pages = "269--272",

journal = "IEE Proceedings: Circuits, Devices and Systems",

issn = "1350-2409",

publisher = "Wiley",

number = "3",

note = "15th International Symposium on Power Semiconductor Devices and ICs 2003, ISPSD 2003 ; Conference date: 14-07-2003 Through 17-07-2003",

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TY - JOUR

T1 - Record low specific on-resistance for low-voltage trench MOSFETs

AU - In't Zandt, M. A.A.

AU - Hijzen, E. A.

AU - Hueting, R. J.E.

AU - Koops, G. E.J.

N1 - Conference code: 15

PY - 2004/6/1

Y1 - 2004/6/1

N2 - A process is shown by which both the specific on-resistance Rds,on and the gate-drain charge density Qgd can be reduced. Reduction of Rds,on is achieved by optimising the channel profile (p-body) towards a more box-shaped profile. Qgd is reduced by reducing the gate-trench widths below the I-line lithography limits, without using deep-UV lithography. For polygonal cell structures, it is shown that trench width reduction also gives further Rds,on reduction. Record values for Rds,on of 4 mΩ · mm2 (at Vgs = 10 V) have been obtained for a 20 V trench MOSFET with a 2 μm cell pitch. Furthermore, for a 30 V trench MOSFET with a 2 μm cell pitch, an Rds,on of 7 mΩ · mm2 (at Vgs = 10 V) was obtained by using a more box-shaped p-body profile.

AB - A process is shown by which both the specific on-resistance Rds,on and the gate-drain charge density Qgd can be reduced. Reduction of Rds,on is achieved by optimising the channel profile (p-body) towards a more box-shaped profile. Qgd is reduced by reducing the gate-trench widths below the I-line lithography limits, without using deep-UV lithography. For polygonal cell structures, it is shown that trench width reduction also gives further Rds,on reduction. Record values for Rds,on of 4 mΩ · mm2 (at Vgs = 10 V) have been obtained for a 20 V trench MOSFET with a 2 μm cell pitch. Furthermore, for a 30 V trench MOSFET with a 2 μm cell pitch, an Rds,on of 7 mΩ · mm2 (at Vgs = 10 V) was obtained by using a more box-shaped p-body profile.

UR - https://www.scopus.com/pages/publications/3042522845

U2 - 10.1049/ip-cds:20040444

DO - 10.1049/ip-cds:20040444

M3 - Conference article

AN - SCOPUS:3042522845

SN - 1350-2409

VL - 151

SP - 269

EP - 272

JO - IEE Proceedings: Circuits, Devices and Systems

JF - IEE Proceedings: Circuits, Devices and Systems

IS - 3

T2 - 15th International Symposium on Power Semiconductor Devices and ICs 2003

Y2 - 14 July 2003 through 17 July 2003

ER -

Record low specific on-resistance for low-voltage trench MOSFETs

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