Recovery of hot-carrier degraded nMOSFETs

Maurits Jelke de Jong

Research output: ThesisPhD Thesis - Research UT, graduation UT

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Nowadays, computer chips are used in all kinds of industries and applications, from communication, transport to health care, and are an important part of our daily lives. The building brick of every computer chip is the transistor, where advancements in transistor technology have led to smaller and faster chips than ever before. Transistors are so important and omnipresent that they are indispensable for keeping our society running.
However, since transistors are getting smaller and smaller and the operation requirements become more severe, computer chips get more susceptible to damage. This results in reduced functionality and ultimately may lead to the failure of the whole computer chip and electronics. Generally, the manufacturers of electronics aim for transistors to function within the specifications for at least ten years. Earlier research had a focus on preventing transistor degradation, or at least minimizing loss in functionality by optimizing material properties, the fabrication process and in some cases the device or chip architecture.
In addition, when it is possible to (partially) repair the transistors, the damage is either prevented/reduced or the defects created in the transistor may be removed completely, resulting in limited and ideally no loss in functionality. Current lifetime predictions do not take repair into account and the possibility of healing a transistor may lead to a device that has a longer operating lifetime, operates at a higher speed and is generally more reliable.
The transistor most commonly used, is the MOSFET (Metal-Oxide Semiconductor Field-Effect-Transistor), where the manufacturer aims to have as few defects present in the device as possible to optimize both the lifetime and operation use. During fabrication, the gate dielectric (the oxide in MOSFET, in this thesis SiO2) is deposited on top of a semiconductor substrate (in this thesis Si). Not all Si atoms at the Si/SiO2-interface can make a bond with atoms in the gate oxide, leading to dangling bonds. Since these dangling bonds can act as a charge trap and may distort various operation parameters, an anneal step in an hydrogen ambient is performed during the fabrication process to passivate the dangling bonds with hydrogen.
Due to hot-carrier injection, the leading degradation mechanism in MOSFETs that takes place during operation, hydrogen start to dissociate at the Si/SiO2-interface, leaving behind defects. This thesis investigates how to repair these hydrogen-related defects, accelerate the recovery process and go back to the initial, fresh state of a device. In a product, the hydrogen that is present in the chip due to the various processing steps can be used to recover the operation induced damage. In this thesis we also investigate the impact of supplying extra hydrogen at various pressures, an effect that mimics the impact of packaging chips in a H-rich environment.
Generally, the recovery of hot-carrier induced damage depends on the amount of hydrogen present for repassivation, the anneal time and anneal temperature. Experiments done in this thesis showed that recovery takes place at temperatures lower than those during fabrication and that an external supply of hydrogen will enhance the recovery rate, even at low pressures (mbar). More recovery was achieved when the hydrogen ambient pressure was increased.
Furthermore, other material considerations, such as a capping layer on top of the device that may act like a diffusion barrier, influence the effective recovery rate.
The recovery seems to fit reasonably well with an earlier model of hydrogen passivation proposed by Stesmans, in which the passivation rate at the Si/SiO2-interface can be described in terms of anneal time, anneal temperature, hydrogen concentration in the device and some material/technology specific parameters. However, experiments showed that Stesmans’ model does not show the whole picture. Subsequent cycles of partial degradation/recovery may lead to a different energy distribution in Si-H bonds, making the recovery of each degradation/recovery cycle different.
Furthermore, hot-carrier injection may also lead to oxide traps. It was found that hydrogen-related defects tend to recover faster/more easily than oxide-related defects. As a consequence, this finding may lead to that after multiple partial degradation/recovery cycles, damage can be attributed more and more to oxide-related traps, where the recovery process behaves according to a different mechanism.
One of the earlier solutions to minimize degradation during the stress phase was to use deuterium instead of hydrogen as a passivation species. These silicon-deuterium bonds at the Si/SiO2-interface are more resilient to hot-carrier stress, which will result in an increased lifetime for the transistor. Experiments described in this thesis suggest that this is only the case for the first degradation cycle. The recovery step may use a combination of hydrogen and deuterium to repassivate the bonds, making the device look more and more like hydrogen passivated devices after subsequent degradation/recovery cycles.
In conclusion, the recovery rate of a hot-carrier degraded transistor is influenced by various parameters like temperature and hydrogen concentration. Various tests have been performed as a first step on the road to a device that can repair itself. However, to induce healing in commercial chips, some of the requirements are that the recovery enhancements should be done internally (no external supply) and at the operation temperature, so that it would not damage the other internal structures of the chip. This would make a self-healing chip viable, that can recover at normal operating temperatures, ultimately leading to a more reliable and potentially faster device.
Original languageEnglish
QualificationDoctor of Philosophy
Awarding Institution
  • University of Twente
  • Schmitz, Jurriaan, Supervisor
  • Salm, Cora, Co-Supervisor
Award date12 May 2022
Place of PublicationEnschede
Print ISBNs978-90-365-5343-8
Publication statusPublished - 2022


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