Reducing Analogue Fault-Simulation Time by Using High-Level Modelling in Dotss for an Industrial Design

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Original language	Undefined
Title of host publication	IEEE Computer Society Proceedings of the ETW
Place of Publication	Stockholm, Sweden
Pages	61-67
Number of pages	7
Publication status	Published - 29 May 2001
Event	6th European Test Workshop, ETW 2001 - Stockholm, Sweden Duration: 29 May 2001 → 1 Jun 2001 Conference number: 6

Conference	6th European Test Workshop, ETW 2001
Abbreviated title	ETW 2001
Country/Territory	Sweden
City	Stockholm
Period	29/05/01 → 1/06/01

Keywords

@inproceedings{be80a6a902c546d69a1a32d08be75ddd,

title = "Reducing Analogue Fault-Simulation Time by Using High-Level Modelling in Dotss for an Industrial Design",

keywords = "METIS-201872",

author = "L. Fang and Guido Gronthoud and Kerkhoff, \{Hans G.\}",

year = "2001",

month = may,

day = "29",

language = "Undefined",

isbn = "0-7695-1017-5",

pages = "61--67",

booktitle = "IEEE Computer Society Proceedings of the ETW",

note = "6th European Test Workshop, ETW 2001 ; Conference date: 29-05-2001 Through 01-06-2001",

}

TY - GEN

T1 - Reducing Analogue Fault-Simulation Time by Using High-Level Modelling in Dotss for an Industrial Design

AU - Fang, L.

AU - Gronthoud, Guido

AU - Kerkhoff, Hans G.

N1 - Conference code: 6

PY - 2001/5/29

Y1 - 2001/5/29

KW - METIS-201872

M3 - Conference contribution

SN - 0-7695-1017-5

SP - 61

EP - 67

BT - IEEE Computer Society Proceedings of the ETW

CY - Stockholm, Sweden

T2 - 6th European Test Workshop, ETW 2001

Y2 - 29 May 2001 through 1 June 2001

ER -