Reducing Generated Clock Jitter by Increasing the PLL Comparison Frequency above the PFD Maximum

  • Bram Nauta (Inventor)
  • , R.C.H. van de Beek (Inventor)
  • , C.S. Vaucher (Inventor)

Research output: Patent

Original languageUndefined
Publication statusSubmitted - 2002

Keywords

  • METIS-205871

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