Reducing MOSFET 1/f Noise and Power Consumption by "Switched Biasing"

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Abstract

Switched biasing is proposed as a technique for reducing the 1/f noise in MOSFET's. Conventional techniques, such as chopping or correlated double sampling, reduce the effect of 1/f noise in electronic circuits, whereas the switched biasing technique reduces the 1/f noise itself. Whereas noise reduction techniques generally lead to more power consumption, switched biasing can reduce the power consumption. It exploits an intriguing physical effect: cycling a MOS transistor from strong inversion to accumulation reduces its intrinsic 1/f noise. As the 1/f noise is reduced at its physical roots, high frequency circuits, in which 1/f noise is being upconverted, can also benefit. This is demonstrated by applying switched biasing in a 0.8 ¿m CMOS sawtooth oscillator. By periodically switching off the bias currents, during time intervals that they are not contributing to the circuit operation, a reduction of the 1/f noise induced phase noise by more than 8 dB is achieved, while the power consumption is also reduced by 30%
Original languageEnglish
Pages (from-to)994-1001
JournalIEEE journal of solid-state circuits
Volume35
Issue number7
DOIs
Publication statusPublished - 2000

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Electric power utilization
Networks (circuits)
Bias currents
MOSFET devices
Phase noise
Noise abatement
Acoustic noise
Sampling

Keywords

  • METIS-111652
  • IR-14526

Cite this

@article{b47a02448f57448295d7681442d158f3,
title = "Reducing MOSFET 1/f Noise and Power Consumption by {"}Switched Biasing{"}",
abstract = "Switched biasing is proposed as a technique for reducing the 1/f noise in MOSFET's. Conventional techniques, such as chopping or correlated double sampling, reduce the effect of 1/f noise in electronic circuits, whereas the switched biasing technique reduces the 1/f noise itself. Whereas noise reduction techniques generally lead to more power consumption, switched biasing can reduce the power consumption. It exploits an intriguing physical effect: cycling a MOS transistor from strong inversion to accumulation reduces its intrinsic 1/f noise. As the 1/f noise is reduced at its physical roots, high frequency circuits, in which 1/f noise is being upconverted, can also benefit. This is demonstrated by applying switched biasing in a 0.8 ¿m CMOS sawtooth oscillator. By periodically switching off the bias currents, during time intervals that they are not contributing to the circuit operation, a reduction of the 1/f noise induced phase noise by more than 8 dB is achieved, while the power consumption is also reduced by 30{\%}",
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author = "Klumperink, {Eric A.M.} and Gierkink, {Sander L.J.} and {van der Wel}, A.P. and Bram Nauta",
year = "2000",
doi = "10.1109/4.848208",
language = "English",
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pages = "994--1001",
journal = "IEEE journal of solid-state circuits",
issn = "0018-9200",
publisher = "IEEE",
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}

Reducing MOSFET 1/f Noise and Power Consumption by "Switched Biasing". / Klumperink, Eric A.M.; Gierkink, Sander L.J.; van der Wel, A.P.; Nauta, Bram.

In: IEEE journal of solid-state circuits, Vol. 35, No. 7, 2000, p. 994-1001.

Research output: Contribution to journalArticleAcademicpeer-review

TY - JOUR

T1 - Reducing MOSFET 1/f Noise and Power Consumption by "Switched Biasing"

AU - Klumperink, Eric A.M.

AU - Gierkink, Sander L.J.

AU - van der Wel, A.P.

AU - Nauta, Bram

PY - 2000

Y1 - 2000

N2 - Switched biasing is proposed as a technique for reducing the 1/f noise in MOSFET's. Conventional techniques, such as chopping or correlated double sampling, reduce the effect of 1/f noise in electronic circuits, whereas the switched biasing technique reduces the 1/f noise itself. Whereas noise reduction techniques generally lead to more power consumption, switched biasing can reduce the power consumption. It exploits an intriguing physical effect: cycling a MOS transistor from strong inversion to accumulation reduces its intrinsic 1/f noise. As the 1/f noise is reduced at its physical roots, high frequency circuits, in which 1/f noise is being upconverted, can also benefit. This is demonstrated by applying switched biasing in a 0.8 ¿m CMOS sawtooth oscillator. By periodically switching off the bias currents, during time intervals that they are not contributing to the circuit operation, a reduction of the 1/f noise induced phase noise by more than 8 dB is achieved, while the power consumption is also reduced by 30%

AB - Switched biasing is proposed as a technique for reducing the 1/f noise in MOSFET's. Conventional techniques, such as chopping or correlated double sampling, reduce the effect of 1/f noise in electronic circuits, whereas the switched biasing technique reduces the 1/f noise itself. Whereas noise reduction techniques generally lead to more power consumption, switched biasing can reduce the power consumption. It exploits an intriguing physical effect: cycling a MOS transistor from strong inversion to accumulation reduces its intrinsic 1/f noise. As the 1/f noise is reduced at its physical roots, high frequency circuits, in which 1/f noise is being upconverted, can also benefit. This is demonstrated by applying switched biasing in a 0.8 ¿m CMOS sawtooth oscillator. By periodically switching off the bias currents, during time intervals that they are not contributing to the circuit operation, a reduction of the 1/f noise induced phase noise by more than 8 dB is achieved, while the power consumption is also reduced by 30%

KW - METIS-111652

KW - IR-14526

U2 - 10.1109/4.848208

DO - 10.1109/4.848208

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VL - 35

SP - 994

EP - 1001

JO - IEEE journal of solid-state circuits

JF - IEEE journal of solid-state circuits

SN - 0018-9200

IS - 7

ER -