Reducing MOSFET 1/f Noise and Power Consumption by 'switched biasing'

Sander L.J. Gierkink, Eric A.M. Klumperink, Adrianus Johannes Maria van Tuijl, Bram Nauta

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    8 Citations (Scopus)
    105 Downloads (Pure)


    "Switched Biasing" is proposed as a new circuit technique that exploits an intriguing physical effect: cycling a MOS transistor between strong inversion and accumulation reduces its intrinsic 1/f noise. The technique is implemented in a 0.8µm CMOS sawtooth oscillator by periodically off-switching of the bias currents during time intervals that they are not contributing to the circuit operation. Measurements show a reduction of the 1/f noise induced phase noise by more than 8 dB, while the power consumption is reduced by more than 30% as well.
    Original languageEnglish
    Title of host publicationProceedings of the 25th European Solid-State Circuits Conference
    Place of PublicationDuisburg, Germany
    Number of pages4
    ISBN (Print)2-86332-246-X
    Publication statusPublished - 21 Sep 1999
    Event25th European Solid-State Circuits Conference, ESSCIRC 1999 - Duisburg, Germany
    Duration: 21 Sep 199923 Sep 1999
    Conference number: 25

    Publication series



    Conference25th European Solid-State Circuits Conference, ESSCIRC 1999
    Abbreviated titleESSCIRC

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