Reducing MOSFET 1/f Noise and Power Consumption by 'switched biasing'

Sander L.J. Gierkink; Eric A.M. Klumperink; Adrianus Johannes Maria van Tuijl; Bram Nauta

Reducing MOSFET 1/f Noise and Power Consumption by 'switched biasing'

Sander L.J. Gierkink
, Eric A.M. Klumperink
, Adrianus Johannes Maria van Tuijl
, Bram Nauta

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

8 Citations (Scopus)

392 Downloads (Pure)

Abstract

"Switched Biasing" is proposed as a new circuit technique that exploits an intriguing physical effect: cycling a MOS transistor between strong inversion and accumulation reduces its intrinsic 1/f noise. The technique is implemented in a 0.8µm CMOS sawtooth oscillator by periodically off-switching of the bias currents during time intervals that they are not contributing to the circuit operation. Measurements show a reduction of the 1/f noise induced phase noise by more than 8 dB, while the power consumption is reduced by more than 30% as well.

Original language	English
Title of host publication	Proceedings of the 25th European Solid-State Circuits Conference
Place of Publication	Duisburg, Germany
Publisher	IEEE
Pages	154-157
Number of pages	4
ISBN (Print)	2-86332-246-X
Publication status	Published - 21 Sept 1999
Event	25th European Solid-State Circuits Conference, ESSCIRC 1999 - Duisburg, Germany Duration: 21 Sept 1999 → 23 Sept 1999 Conference number: 25

Publication series

Name
Publisher	IEEE

Conference

Conference	25th European Solid-State Circuits Conference, ESSCIRC 1999
Abbreviated title	ESSCIRC
Country/Territory	Germany
City	Duisburg
Period	21/09/99 → 23/09/99

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@inproceedings{3c6a772d94ee4c02beee4d16718ea9dd,

title = "Reducing MOSFET 1/f Noise and Power Consumption by 'switched biasing'",

abstract = "{"}Switched Biasing{"} is proposed as a new circuit technique that exploits an intriguing physical effect: cycling a MOS transistor between strong inversion and accumulation reduces its intrinsic 1/f noise. The technique is implemented in a 0.8µm CMOS sawtooth oscillator by periodically off-switching of the bias currents during time intervals that they are not contributing to the circuit operation. Measurements show a reduction of the 1/f noise induced phase noise by more than 8 dB, while the power consumption is reduced by more than 30\% as well.",

author = "Gierkink, \{Sander L.J.\} and Klumperink, \{Eric A.M.\} and \{van Tuijl\}, \{Adrianus Johannes Maria\} and Bram Nauta",

year = "1999",

month = sep,

day = "21",

language = "English",

isbn = "2-86332-246-X",

publisher = "IEEE",

pages = "154--157",

booktitle = "Proceedings of the 25th European Solid-State Circuits Conference",

address = "United States",

note = "25th European Solid-State Circuits Conference, ESSCIRC 1999, ESSCIRC ; Conference date: 21-09-1999 Through 23-09-1999",

}

Reducing MOSFET 1/f Noise and Power Consumption by 'switched biasing'. / Gierkink, Sander L.J.; Klumperink, Eric A.M.; van Tuijl, Adrianus Johannes Maria et al.
Proceedings of the 25th European Solid-State Circuits Conference. Duisburg, Germany: IEEE, 1999. p. 154-157.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - Reducing MOSFET 1/f Noise and Power Consumption by 'switched biasing'

AU - Gierkink, Sander L.J.

AU - Klumperink, Eric A.M.

AU - van Tuijl, Adrianus Johannes Maria

AU - Nauta, Bram

N1 - Conference code: 25

PY - 1999/9/21

Y1 - 1999/9/21

N2 - "Switched Biasing" is proposed as a new circuit technique that exploits an intriguing physical effect: cycling a MOS transistor between strong inversion and accumulation reduces its intrinsic 1/f noise. The technique is implemented in a 0.8µm CMOS sawtooth oscillator by periodically off-switching of the bias currents during time intervals that they are not contributing to the circuit operation. Measurements show a reduction of the 1/f noise induced phase noise by more than 8 dB, while the power consumption is reduced by more than 30% as well.

AB - "Switched Biasing" is proposed as a new circuit technique that exploits an intriguing physical effect: cycling a MOS transistor between strong inversion and accumulation reduces its intrinsic 1/f noise. The technique is implemented in a 0.8µm CMOS sawtooth oscillator by periodically off-switching of the bias currents during time intervals that they are not contributing to the circuit operation. Measurements show a reduction of the 1/f noise induced phase noise by more than 8 dB, while the power consumption is reduced by more than 30% as well.

M3 - Conference contribution

SN - 2-86332-246-X

SP - 154

EP - 157

BT - Proceedings of the 25th European Solid-State Circuits Conference

PB - IEEE

CY - Duisburg, Germany

T2 - 25th European Solid-State Circuits Conference, ESSCIRC 1999

Y2 - 21 September 1999 through 23 September 1999

ER -

Reducing MOSFET 1/f Noise and Power Consumption by 'switched biasing'

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