Error correction codes (ECCs) are commonly used to protect memory devices from errors. The most commonly used codes are a simple parity bit and single-error-correction (SEC) codes. A parity bit enables single-bit error detection, whereas a SEC code can correct one-bit errors. A SEC code requires more additional bits per word and also more complex decoding that impacts delay. A tradeoff between both schemes is the use of a product code based on a combination of two parity bits. This approach reduces the memory overhead at the expense of a more complex access procedure. In this letter, an alternative scheme based on the use of parity sharing is proposed and evaluated. The results show that the new approach significantly reduces the memory overhead and is also capable of correcting single-bit errors.
|Journal||IEEE transactions on device and materials reliability|
|Publication status||Published - 2013|