Reducing the Susceptibility of Design-for-Delay-Testability Structures to Process- and Application-Induced Variations

H.J. Vermaak; H.G. Kerkhoff

doi:10.1109/ETW.2001.946658

Reducing the Susceptibility of Design-for-Delay-Testability Structures to Process- and Application-Induced Variations

H.J. Vermaak
, H.G. Kerkhoff

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

1 Citation (Scopus)

Abstract

Recently, a new type of Design-for-Delay-Testability structure and associated Built-In Self-Test architecture for detecting delay faults in digital high-performance circuits has been proposed. It circumvents the requirement of an expensive high-speed tester. In this paper, the susceptibility of the proposed structure to process- and application-induced variations has been investigated Due to the critical timing necessary when detecting small delay faults it is crucial to know what to expect +om these variations and subsequently reduce their influence.

Original language	English
Title of host publication	IEEE European Test Workshop 2001
Place of Publication	Piscataway, NJ
Publisher	IEEE
Pages	35-41
Number of pages	7
ISBN (Print)	0-7695-1017-5
DOIs	https://doi.org/10.1109/ETW.2001.946658
Publication status	Published - 29 May 2001
Event	6th European Test Workshop, ETW 2001 - Stockholm, Sweden Duration: 29 May 2001 → 1 Jun 2001 Conference number: 6

Publication series

Name	Proceedings IEEE European Test Workshop
Publisher	IEEE
Volume	2001
ISSN (Print)	1530-1877

Conference

Conference	6th European Test Workshop, ETW 2001
Abbreviated title	ETW 2001
Country/Territory	Sweden
City	Stockholm
Period	29/05/01 → 1/06/01

Access to Document

10.1109/ETW.2001.946658

Cite this

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title = "Reducing the Susceptibility of Design-for-Delay-Testability Structures to Process- and Application-Induced Variations",

abstract = "Recently, a new type of Design-for-Delay-Testability structure and associated Built-In Self-Test architecture for detecting delay faults in digital high-performance circuits has been proposed. It circumvents the requirement of an expensive high-speed tester. In this paper, the susceptibility of the proposed structure to process- and application-induced variations has been investigated Due to the critical timing necessary when detecting small delay faults it is crucial to know what to expect +om these variations and subsequently reduce their influence.",

author = "H.J. Vermaak and H.G. Kerkhoff",

year = "2001",

month = may,

day = "29",

doi = "10.1109/ETW.2001.946658",

language = "English",

isbn = "0-7695-1017-5",

series = "Proceedings IEEE European Test Workshop",

publisher = "IEEE",

pages = "35--41",

booktitle = "IEEE European Test Workshop 2001",

address = "United States",

note = "6th European Test Workshop, ETW 2001, ETW 2001 ; Conference date: 29-05-2001 Through 01-06-2001",

}

Vermaak, HJ & Kerkhoff, HG 2001, Reducing the Susceptibility of Design-for-Delay-Testability Structures to Process- and Application-Induced Variations. in IEEE European Test Workshop 2001. Proceedings IEEE European Test Workshop, vol. 2001, IEEE, Piscataway, NJ, pp. 35-41, 6th European Test Workshop, ETW 2001, Stockholm, Sweden, 29/05/01. https://doi.org/10.1109/ETW.2001.946658

Reducing the Susceptibility of Design-for-Delay-Testability Structures to Process- and Application-Induced Variations. / Vermaak, H.J.; Kerkhoff, H.G.
IEEE European Test Workshop 2001. Piscataway, NJ: IEEE, 2001. p. 35-41 (Proceedings IEEE European Test Workshop; Vol. 2001).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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N2 - Recently, a new type of Design-for-Delay-Testability structure and associated Built-In Self-Test architecture for detecting delay faults in digital high-performance circuits has been proposed. It circumvents the requirement of an expensive high-speed tester. In this paper, the susceptibility of the proposed structure to process- and application-induced variations has been investigated Due to the critical timing necessary when detecting small delay faults it is crucial to know what to expect +om these variations and subsequently reduce their influence.

AB - Recently, a new type of Design-for-Delay-Testability structure and associated Built-In Self-Test architecture for detecting delay faults in digital high-performance circuits has been proposed. It circumvents the requirement of an expensive high-speed tester. In this paper, the susceptibility of the proposed structure to process- and application-induced variations has been investigated Due to the critical timing necessary when detecting small delay faults it is crucial to know what to expect +om these variations and subsequently reduce their influence.

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DO - 10.1109/ETW.2001.946658

M3 - Conference contribution

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T3 - Proceedings IEEE European Test Workshop

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BT - IEEE European Test Workshop 2001

PB - IEEE

CY - Piscataway, NJ

T2 - 6th European Test Workshop, ETW 2001

Y2 - 29 May 2001 through 1 June 2001

ER -

Reducing the Susceptibility of Design-for-Delay-Testability Structures to Process- and Application-Induced Variations

Abstract

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Conference

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