Abstract
| Original language | English |
|---|---|
| Title of host publication | Partial-Order Reduzierung des Zustandsraumes bei der BDD-Modellprüfung |
| Subtitle of host publication | GI/ITG-Fachgespräch, 19. - 20. Juni 1997 in Berlin |
| Editors | A. Wolisz, I. Schieferdecker, A. Rennoch |
| Place of Publication | Sankt Augustin |
| Publisher | GMD-Forschungszentrum Informationstechnik GmbH |
| Pages | 23-37 |
| Number of pages | 15 |
| ISBN (Print) | 3-88457-315-2 |
| Publication status | Published - Jun 1997 |
| Event | Formale Beschreibungstechniken für verteilte Systeme 1997: GI/ITG-Fachgespräch - Berlin, Germany Duration: 19 Jun 1997 → 20 Jun 1997 |
Publication series
| Name | GMD Studien |
|---|---|
| Publisher | GMD-Forschungszentrum Informationstechnik GmbH |
| Volume | 315 |
Workshop
| Workshop | Formale Beschreibungstechniken für verteilte Systeme 1997 |
|---|---|
| Country | Germany |
| City | Berlin |
| Period | 19/06/97 → 20/06/97 |
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Keywords
- FMT-TESTING
Cite this
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Repetitive Quiescence in Implementation and Testing (Extended Abstract). / Tretmans, G.J.
Partial-Order Reduzierung des Zustandsraumes bei der BDD-Modellprüfung: GI/ITG-Fachgespräch, 19. - 20. Juni 1997 in Berlin. ed. / A. Wolisz; I. Schieferdecker; A. Rennoch. Sankt Augustin : GMD-Forschungszentrum Informationstechnik GmbH, 1997. p. 23-37 (GMD Studien; Vol. 315).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
TY - GEN
T1 - Repetitive Quiescence in Implementation and Testing (Extended Abstract)
AU - Tretmans, G.J.
PY - 1997/6
Y1 - 1997/6
N2 - This paper studies implementation relations and testing based on labelled transition sys- tems, using the assumption that implementations communicate with their environment via inputs and outputs. Such implementations are formalized by restricting the class of transition systems to those systems that can always accept input actions. Implementation relations, which formalize the notion of correctness of these implementations with respect to labelled transition system specifications, are defined analogous to the theories of testing equivalence and preorder, and refusal testing. A test generation algorithm is given, which is proved to produce a sound and exhaustive test suite from a specification, i.e., a test suite that fully characterizes the set of correct implementations.
AB - This paper studies implementation relations and testing based on labelled transition sys- tems, using the assumption that implementations communicate with their environment via inputs and outputs. Such implementations are formalized by restricting the class of transition systems to those systems that can always accept input actions. Implementation relations, which formalize the notion of correctness of these implementations with respect to labelled transition system specifications, are defined analogous to the theories of testing equivalence and preorder, and refusal testing. A test generation algorithm is given, which is proved to produce a sound and exhaustive test suite from a specification, i.e., a test suite that fully characterizes the set of correct implementations.
KW - FMT-TESTING
M3 - Conference contribution
SN - 3-88457-315-2
T3 - GMD Studien
SP - 23
EP - 37
BT - Partial-Order Reduzierung des Zustandsraumes bei der BDD-Modellprüfung
A2 - Wolisz, A.
A2 - Schieferdecker, I.
A2 - Rennoch, A.
PB - GMD-Forschungszentrum Informationstechnik GmbH
CY - Sankt Augustin
ER -