Revisiting Resistance Speeds Up I/O-Efficient LTL Model Checking

J. Barnat, L. Brim, P. Šimeček, M. Weber

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    20 Citations (Scopus)

    Abstract

    Revisiting resistant graph algorithms are those that can tolerate re-exploration of edges without yielding incorrect results. Revisiting resistant I/O efficient graph algorithms exhibit considerable speed-up in practice in comparison to non-revisiting resistant algorithms. In the paper we present a new revisiting resistant I/O efficient LTL model checking algorithm. We analyze its theoretical I/O complexity and we experimentally compare its performance to already existing I/O efficient LTL model checking algorithms.
    Original languageUndefined
    Title of host publication14th International Conference on Tools and Algorithms for the Construction and Analysis of Systems, TACAS 2008
    EditorsC.R. Ramakrishnan, J Rehof
    Place of PublicationLondon
    PublisherSpringer
    Pages48-62
    Number of pages14
    ISBN (Print)978-3-540-78799-0
    DOIs
    Publication statusPublished - Mar 2008

    Publication series

    NameLecture Notes in Computer Science
    PublisherSpringer Verlag
    Number302
    Volume4963
    ISSN (Print)0302-9743
    ISSN (Electronic)1611-3349

    Keywords

    • EWI-12954
    • METIS-251039
    • IR-62369

    Cite this

    Barnat, J., Brim, L., Šimeček, P., & Weber, M. (2008). Revisiting Resistance Speeds Up I/O-Efficient LTL Model Checking. In C. R. Ramakrishnan, & J. Rehof (Eds.), 14th International Conference on Tools and Algorithms for the Construction and Analysis of Systems, TACAS 2008 (pp. 48-62). [10.1007/978-3-540-78800-3_5] (Lecture Notes in Computer Science; Vol. 4963, No. 302). London: Springer. https://doi.org/10.1007/978-3-540-78800-3_5