RF building block modeling: optimization and synthesis

For circuit designers it is desirable to have relatively simple RF circuit models that do give decent estimation accuracy and provide sufficient understanding of circuits. Chapter 2 in this thesis shows a general weak nonlinearity model that meets these demands. Using a method that is related to harmonic balance, this model yields closed-form expressions that are a linear combination of technology dependent transistor nonlinearity parameters and topology-dependent AC transfer functions only. Using this, time-invariant weakly nonlinear analyses can be accomplished using time-invariant linear analyses. This general distortion model is used in this thesis to derive design insights and novel methods to cancel distortion in attenuator and in cascoded LNAs. Chapter 3 presents a proof-of-concept resistive feedback LNA fabricated in a standard 0.16µm CMOS process, for 0.1GHz to 1GHz, showing improve-ments of 6.3dB to 10dB for IIP3 and 0.2dB to 1dB for gain without noise degradation and with a very modest power and area penalty. Chapter 4 shows distortion cancellation for CMOS attenuators: in the demonstration T-attenuator system, for DC-5GHz, >3dBm input P1dB and >26dBm IIP3 are achieved in measurements, while the active area is 0.0054mm2. Similar performance is achieved in the T-attenuator system. Both simulation and measurement results demonstrate good robustness against PVT variations. Using the introduced analysis method in chapter 5, the noise and distortion of this time-varying system are estimated by a limited number of time-invariant AC calculations. The analyses show that the decreasing transistor output resistance together with the low supply voltage in deep submicron technologies contributes significantly to flicker-noise leakage. The analyses also show that the slope of the LO signal has significant effect on IIP2 while little effect on IIP3. Chapter 6 presents techniques to simultaneously cancel flicker noise and IM3 in Gilbert-type mixers. One demonstration chip is designed for full-IM3/partial-flicker-noise cancellation at 0.9GHz, which achieves 9dB flicker noise suppression, improvements of 10dB for IIP3, 5dB for conversion gain, and 1dB for input P1dB while the thermal noise increased by 0.1dB at the cost of a small power and area penalty. The overall conclusion and suggestion for future work are summarized in chapter 7.