RF CMOS reliability simulations

G.T. Sasse, M. Acar, F.G. Kuper, Jurriaan Schmitz

    Research output: Contribution to journalArticleAcademicpeer-review

    16 Citations (Scopus)

    Abstract

    We present a simulation approach to assess the reliability of an RF CMOS circuit under user conditions, based on existing DC degradation models for gate-oxide breakdown and hot-carrier degradation. The simulator allows for lifetime prediction of circuits that can withstand multiple breakdown events. Simulation results show that three power amplifiers with comparable initial circuit performance show an astronomic difference in reliability. The tool thus proves to be an asset in the analog design process.
    Original languageUndefined
    Article number10.1016/j.microrel.2008.06.017
    Pages (from-to)1581-1585
    Number of pages5
    JournalMicroelectronics reliability
    Volume48
    Issue numberWoTUG-31/8-9
    DOIs
    Publication statusPublished - 23 Aug 2008

    Keywords

    • IR-62596
    • METIS-254979
    • SC-ICRY: Integrated Circuit Reliability and Yield
    • EWI-14574

    Cite this

    Sasse, G. T., Acar, M., Kuper, F. G., & Schmitz, J. (2008). RF CMOS reliability simulations. Microelectronics reliability, 48(WoTUG-31/8-9), 1581-1585. [10.1016/j.microrel.2008.06.017]. https://doi.org/10.1016/j.microrel.2008.06.017