RF Spectrum sensing in CMOS Exploiting Crosscorrelation

The introduction of new wireless services, the demand for higher datarates, and higher traffic volumes call for a more efficient use of the RF spectrum than what is currently possible with static frequency allocation. Dynamic spectrum access offers a more efficient use by allowing unlicensed users to opportunistically use locally and temporarily unoccupied licensed bands (‘white space’). To prevent harmful interference to the licensed users, unlicensed users need tomake sure the band is free before they are allowed to transmit. This means that, if resorting to databases is not possible or desired, the unlicensed users have to be able to detect very weak signals from the licensed users by means of spectrum sensing. Different types of spectrum sensing exist, but it is preferable to use one that does not require knowledge of the signals to be detected, as it can then be employed in arbitrary frequency bands. Such a solution is energy detection (ED). The first step of ED is similar to what a spectrum analyzer (SA) does: measure the power in a frequency band. The second step is to distinguish between measuring only noise, or noise plus a signal. Due to inaccuracies in the noise level estimation, there is a certain minimum signal-to-noise ratio (SNR), the SNR-wall, below which signals cannot be reliably detected. Several analog impairments, such as phase noise, nonlinearity, and limited harmonic rejection (HR), can also hamper the detection process by causing false alarms or missed detections. To reduce the SNR-wall and the influence of analog impairments on sensing performance, crosscorrelation (XC) spectrum sensing, as a generalization of autocorrelation (AC) (the standard form of ED), is proposed. XC multiplies and integrates the outputs of two receivers, each processing the same signal, to obtain the signal power, while the noise (ideally) averages out. The noise uncertainty is removed at the cost ofmeasurement time, and the SNR-wall reduces. A mathematical model is developed that predicts that (1) a lower noise correlation between the two receivers lowers the SNR-wall, and (2) resistive attenuation at the input of each receiver does not influence the sensitivity of XC. This allows a design to be optimized for high linearity without affecting the detection capabilities. By employing a separate oscillator for each receiver, XC can also reduce phase noise. A frequency offset between the two oscillators, in combination with some digital signal processing, also allows XC to improve HR. A first mostly-discrete prototype is developed, employing a mixer-first architecture for high linearity. It demonstrates (phase) noise reduction and an attenuation-independent noise floor using XC, but suffers from external frequency-dependent coupling between the receivers, crosstalk between the mixers, and a poor HR. A second protype tackles these disadvantages by integrating two RF-frontends into a single 1.2V 65nm CMOS-chip, with a novel distortion-cancellation technique in the attenuators for high linearity. Measurements show that XC achieves 22 dB of phase noise reduction (limited by measurement time), and up to 25 dB of improvement in HR (limited by crosstalk). At 10 dB attenuation, the SNR-wall is found to be -184 dBm/Hz, which is 10 dB below the thermal noise floor, and even 12 dB below the measured SNR-wall of AC. XC achieves an attenuationindependent noise floor < -169 dBm/Hz from 0.3–1.0 GHz, with an IIP3 of +25dBm at 10 dB attenuation, which makes the spurious-free dynamic range higher than that of high-end commercial SAs. Furthermore, it is experimentally shown that XC can be much faster and more energy-efficient than AC. Overall, XC is shown to enable the integration of SAs with high sensitivity, good resilience to strong interferers, and with speed and, at low SNR, energy consumption benefits compared to AC. This not only makes sensitive spectrum sensing attainable in a hostile radio environment, but also paves the way for low-cost, low-power, and high-quality (mobile)measurement equipment. Furthermore, it may enable the integration of (many) small SAs inside other chips for built-in self-test (BIST), reducing on pin count and test time during manufacturing, as well as more reliable and stable performance during operation.