Software-defined radio receivers increasingly exploit linear RF V-I conversion, instead of RF voltage gain, to improve interference robustness. Unfortunately, the linearity of CMOS inverters, which are often used to implement V-I conversion, is highly sensitive to Process, Voltage and Temperature variations. This paper proposes a more robust technique based on resistive degeneration. To mitigate third-order IM3 distortion induced by the quadratic MOSFET I-V characteristic, a new linearization technique is proposed which exploits a floating battery by-pass circuit and replica biasing to improve IIP3 in a robust way. This paper explains the concept and analyzes linearity improvement. To demonstrate operation, an LNTA with current domain mixer is implemented in a 45 nm CMOS process. Compared to a conventional inverter based LNTA with the same transconductance, it improves IIP3 from 2 dBm to a robust PIIP3 of 8 dBm at the cost of 67% increase in power consumption.