RIE lag in high aspect ratio trench etching of silicon

Henri Jansen (Corresponding Author), Meint de Boer, Remco Wiegerink, Niels Tas, Edwin Smulders, Cristina Neagu, Miko Elwenspoek

    Research output: Contribution to journalConference articleAcademicpeer-review

    96 Citations (Scopus)
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    Abstract

    While etching high aspect ratio trenches into silicon with reactive ion etching (RIE) using an SF6/O2 chemistry it is observed that the etch rate is depending on the mask opening. This effect is known as RIE lag and is caused by the depletion of etching ions and radicals or inhibiting neutrals during their trench passage. In order to decide which source is the main cause, we constructed special 'horizontal trenches' where only radicals are controlling the etching. The experiment showed that radicals are not responsible for RIE lag. Inhibitor depletion will result in inverse RIE lag. This effect is not found during our experimentation which leaves us with ion depletion to explain RIE lag. Depletion of ions is caused by ions captured by the sidewalls due to the angular distribution of incoming ions into the trench opening and the deflection of ions in the trench due to electrostatic fields. The analysis given in this paper indicates that the influencing field causes ion deflection, ion depletion, and therefore RIE lag in micron-sized Si trenches for low-energetic ions. In all cases, thus independent of the feature size, the angular distribution of incoming ions is thought to have a major contribution to RIE lag at higher pressures. These phenomena will be treated theoretically and simulated using a program, written in c++ under windows, in order to give a quantitative analysis of RIE lag.
    Original languageEnglish
    Pages (from-to)45-50
    Number of pages6
    JournalMicroelectronic engineering
    Volume35
    Issue number1-4
    DOIs
    Publication statusPublished - Feb 1997
    Event22nd International Conference on Micro- and Nano-Engineering, MNE 1996
    - Glasgow, United Kingdom
    Duration: 22 Sep 199625 Sep 1996
    Conference number: 22

    Fingerprint

    Reactive ion etching
    Silicon
    high aspect ratio
    Aspect ratio
    Etching
    time lag
    etching
    Ions
    silicon
    ions
    Angular distribution
    depletion
    Corrosion inhibitors
    deflection
    angular distribution
    Masks
    Electric fields
    causes
    experimentation

    Cite this

    Jansen, Henri ; de Boer, Meint ; Wiegerink, Remco ; Tas, Niels ; Smulders, Edwin ; Neagu, Cristina ; Elwenspoek, Miko. / RIE lag in high aspect ratio trench etching of silicon. In: Microelectronic engineering. 1997 ; Vol. 35, No. 1-4. pp. 45-50.
    @article{943974dda41148eda337c0381cf9482e,
    title = "RIE lag in high aspect ratio trench etching of silicon",
    abstract = "While etching high aspect ratio trenches into silicon with reactive ion etching (RIE) using an SF6/O2 chemistry it is observed that the etch rate is depending on the mask opening. This effect is known as RIE lag and is caused by the depletion of etching ions and radicals or inhibiting neutrals during their trench passage. In order to decide which source is the main cause, we constructed special 'horizontal trenches' where only radicals are controlling the etching. The experiment showed that radicals are not responsible for RIE lag. Inhibitor depletion will result in inverse RIE lag. This effect is not found during our experimentation which leaves us with ion depletion to explain RIE lag. Depletion of ions is caused by ions captured by the sidewalls due to the angular distribution of incoming ions into the trench opening and the deflection of ions in the trench due to electrostatic fields. The analysis given in this paper indicates that the influencing field causes ion deflection, ion depletion, and therefore RIE lag in micron-sized Si trenches for low-energetic ions. In all cases, thus independent of the feature size, the angular distribution of incoming ions is thought to have a major contribution to RIE lag at higher pressures. These phenomena will be treated theoretically and simulated using a program, written in c++ under windows, in order to give a quantitative analysis of RIE lag.",
    author = "Henri Jansen and {de Boer}, Meint and Remco Wiegerink and Niels Tas and Edwin Smulders and Cristina Neagu and Miko Elwenspoek",
    year = "1997",
    month = "2",
    doi = "10.1016/S0167-9317(96)00142-6",
    language = "English",
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    }

    Jansen, H, de Boer, M, Wiegerink, R, Tas, N, Smulders, E, Neagu, C & Elwenspoek, M 1997, 'RIE lag in high aspect ratio trench etching of silicon', Microelectronic engineering, vol. 35, no. 1-4, pp. 45-50. https://doi.org/10.1016/S0167-9317(96)00142-6

    RIE lag in high aspect ratio trench etching of silicon. / Jansen, Henri (Corresponding Author); de Boer, Meint; Wiegerink, Remco; Tas, Niels; Smulders, Edwin; Neagu, Cristina; Elwenspoek, Miko.

    In: Microelectronic engineering, Vol. 35, No. 1-4, 02.1997, p. 45-50.

    Research output: Contribution to journalConference articleAcademicpeer-review

    TY - JOUR

    T1 - RIE lag in high aspect ratio trench etching of silicon

    AU - Jansen, Henri

    AU - de Boer, Meint

    AU - Wiegerink, Remco

    AU - Tas, Niels

    AU - Smulders, Edwin

    AU - Neagu, Cristina

    AU - Elwenspoek, Miko

    PY - 1997/2

    Y1 - 1997/2

    N2 - While etching high aspect ratio trenches into silicon with reactive ion etching (RIE) using an SF6/O2 chemistry it is observed that the etch rate is depending on the mask opening. This effect is known as RIE lag and is caused by the depletion of etching ions and radicals or inhibiting neutrals during their trench passage. In order to decide which source is the main cause, we constructed special 'horizontal trenches' where only radicals are controlling the etching. The experiment showed that radicals are not responsible for RIE lag. Inhibitor depletion will result in inverse RIE lag. This effect is not found during our experimentation which leaves us with ion depletion to explain RIE lag. Depletion of ions is caused by ions captured by the sidewalls due to the angular distribution of incoming ions into the trench opening and the deflection of ions in the trench due to electrostatic fields. The analysis given in this paper indicates that the influencing field causes ion deflection, ion depletion, and therefore RIE lag in micron-sized Si trenches for low-energetic ions. In all cases, thus independent of the feature size, the angular distribution of incoming ions is thought to have a major contribution to RIE lag at higher pressures. These phenomena will be treated theoretically and simulated using a program, written in c++ under windows, in order to give a quantitative analysis of RIE lag.

    AB - While etching high aspect ratio trenches into silicon with reactive ion etching (RIE) using an SF6/O2 chemistry it is observed that the etch rate is depending on the mask opening. This effect is known as RIE lag and is caused by the depletion of etching ions and radicals or inhibiting neutrals during their trench passage. In order to decide which source is the main cause, we constructed special 'horizontal trenches' where only radicals are controlling the etching. The experiment showed that radicals are not responsible for RIE lag. Inhibitor depletion will result in inverse RIE lag. This effect is not found during our experimentation which leaves us with ion depletion to explain RIE lag. Depletion of ions is caused by ions captured by the sidewalls due to the angular distribution of incoming ions into the trench opening and the deflection of ions in the trench due to electrostatic fields. The analysis given in this paper indicates that the influencing field causes ion deflection, ion depletion, and therefore RIE lag in micron-sized Si trenches for low-energetic ions. In all cases, thus independent of the feature size, the angular distribution of incoming ions is thought to have a major contribution to RIE lag at higher pressures. These phenomena will be treated theoretically and simulated using a program, written in c++ under windows, in order to give a quantitative analysis of RIE lag.

    U2 - 10.1016/S0167-9317(96)00142-6

    DO - 10.1016/S0167-9317(96)00142-6

    M3 - Conference article

    VL - 35

    SP - 45

    EP - 50

    JO - Microelectronic engineering

    JF - Microelectronic engineering

    SN - 0167-9317

    IS - 1-4

    ER -