Rise-time effects in ggnMOSt under TLP stress

G. Boselli, A.J. Mouthaan, F.G. Kuper

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    Abstract

    In this paper the main mechanisms that lead the turn on of the parasitic bipolar transistor of a grounded gate nMOS transistor (ggnMOS) under TLP stress have been analyzed in detail in the sub-nanoseconds range by means of a mixed-mode simulator. We showed that the breakdown voltage of the ggnMOS measured in static conditions would underestimate the maximum voltage across the protection structure obtained by TLP stress, depending on the rise-time of the applied pulse
    Original languageUndefined
    Title of host publicationProceedings of 22nd international conference on microelectronics
    Place of PublicationNis, Yugoslavia
    PublisherIEEE
    Pages355-357
    ISBN (Print)0780352351
    DOIs
    Publication statusPublished - 14 May 2000
    Event22nd International Conference on Microelectronics, 2000 - Nis, Yugoslavia
    Duration: 14 May 200017 May 2000

    Publication series

    Name
    PublisherIEEE
    Volume1

    Conference

    Conference22nd International Conference on Microelectronics, 2000
    Period14/05/0017/05/00
    Other14-17 May 2000

    Keywords

    • METIS-113961
    • IR-17073

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