Rise-time effects in ggnMOSt under TLP stress

In this paper, the clamping voltage of a grounded gate nMOS transistor (ggnMOSt) under transmission line pulse (TLP) stress has been analysed in detail by means of a mixed-mode simulator. We show that the breakdown voltage of the ggnMOSt measured in static conditions could underestimate the maximum voltage across the protection structure obtained by TLP stress, depending on the rise time of the applied pulse. In particular, the smaller the rise time, the larger the peak reached for the drain voltage. In this paper, we will show that this can be attributed to the charging of the overlap capacitance. The influence of the LDD implant option with respect to the standard implant has also been investigated. The relationship between the maximum clamping voltage and the triggering voltage of the parasitic bipolar transistor associated with the structure is explained. A simple analytical model describing the response of the device in the early phase of the forced pulse is presented.